DJLXT972ALC.A4 Cortina Systems Inc, DJLXT972ALC.A4 Datasheet - Page 32

• Manufacturer Part Number: DJLXT972ALC.A4
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT972ALC.A4

• Lead Free Status / RoHS Status: Not Compliant

LXT972A PHY
Datasheet
249186, Revision 5.2
13 September 2007
Figure 8
Figure 9
5.6.2
5.6.3
Cortina Systems
Clocking for 100BASE-X
Clocking for Link Down Clock Transition
Transmit Enable
The MAC must assert TX_EN the same time as the first nibble of preamble and de-assert
TX_EN after the last nibble of the packet.
Receive Data Valid
The LXT972A PHY asserts RX_DV when it receives a valid packet. Timing changes
depend on line operating speed:
®
TX_CLK
RX_CLK
XI
• For 100BASE-TX links, RX_DV is asserted from the first nibble of preamble to the last
• For 10BASE-T links, the entire preamble is truncated. RX_DV is asserted with the first
LXT972A Single-Port 10/100 Mbps PHY Transceiver
nibble of the data packet.
nibble of the Start of Frame Delimiter (SFD) “5D” and remains asserted until the end
of the packet.
RX_CLK
TX_CLK
2.5 MHz during auto-negotiation
2.5 MHz during auto-negotiation
Clock
Any
Clock transition time does not exceed
2X the nominal clock period:
10 Mbps = 2.5 MHz
100 Mbps = 25 MHz
Constant 25 MHz
Link-Down Condition/Auto-Negotiate Enabled
2.5 MHz
Clock
B3503-01
25 MHz once 100BASE-X
25 MHz once 100BASE-X
Link Established
Link Established
5.6 MII Operation
B3391-01
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