DJLXT972ALC.A4 Cortina Systems Inc, DJLXT972ALC.A4 Datasheet - Page 56

• Manufacturer Part Number: DJLXT972ALC.A4
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT972ALC.A4

• Lead Free Status / RoHS Status: Not Compliant

LXT972A PHY
Datasheet
249186, Revision 5.2
13 September 2007
Table 30
Figure 23
Cortina Systems
100BASE-TX Receive Timing Parameters - 4B Mode
100BASE-TX Transmit Timing
®
RXD[3:0], RX_DV, RX_ER
RX_CLK High
RXD[3:0], RX_DV, RX_ER hold
from RX_CLK High
CRS asserted to RXD[3:0], RX_DV
Receive start of “J” to CRS asserted
Receive start of “T” to CRS de-asserted
Receive start of “J” to COL asserted
Receive start of “T” to COL de-asserted
1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production
2. BT (Bit Time) is the duration of one bit as transferred to and from the Mac and is the reciprocal of the bit
3. RX_ER is not shown in the figure.
LXT972A Single-Port 10/100 Mbps PHY Transceiver
testing.
rate. 100BASE-T bit time = 10
Parameter
TXD[3:0]
Note: Timing diagram depicts 4B mode.
TXCLK
TX_EN
CRS
TPO
0ns
3
setup to
-8
s or 10 ns.
t3
t5
t2
t1
Sym
t1
t2
t3
t4
t5
t6
t7
Min
10
10
12
10
16
17
3
Typ
–
–
–
–
–
–
–
1
250ns
t4
Max
16
17
22
20
–
–
5
7.2 AC Timing Diagrams and
Units
B3454-03
BT
BT
BT
BT
BT
ns
ns
2
Test Conditions
Parameters
–
–
–
–
–
–
–
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