DJLXT972ALC.A4 Cortina Systems Inc, DJLXT972ALC.A4 Datasheet - Page 38
DJLXT972ALC.A4
Manufacturer Part Number
DJLXT972ALC.A4
Description
Manufacturer
Cortina Systems Inc
Datasheet
1.DJLXT972ALC.A4.pdf
(80 pages)
Specifications of DJLXT972ALC.A4
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LXT972A PHY
Datasheet
249186, Revision 5.2
13 September 2007
5.7.3
Figure 17
5.7.3.1
5.7.3.1.1
Cortina Systems
100BASE-X Protocol Sublayer Operations
With respect to the 7-layer communications model, the LXT972A PHY is a Physical Layer
1 (PHY) device.
The LXT972A PHY implements the following sublayers of the reference model defined by
the IEEE 802.3 standard, and discussed from the reference model point of view:
Figure 17
Protocol Sublayers
Physical Coding Sublayer
The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B
encoding/decoding function.
For 100BASE-TX operation, the PCS layer provides IDLE symbols to the PMD-layer line
driver as long as TX_EN is de-asserted.
Preamble Handling
When the MAC asserts TX_EN, the PCS substitutes a /J/K symbol pair, also known as the
Start-of-Stream Delimiter (SSD), for the first two nibbles received across the MII. The PCS
layer continues to encode the remaining MII data, following the 4B/5B coding in
until TX_EN is de-asserted. It then returns to supplying IDLE symbols to the line driver.
®
•
•
•
LXT972A Single-Port 10/100 Mbps PHY Transceiver
Sublayer
Sublayer
Sublayer
Section 5.7.3.1, Physical Coding Sublayer
Section 5.7.3.2, Physical Medium Attachment Sublayer
Section 5.7.3.3, Twisted-Pair Physical Medium Dependent Sublayer
PMA
PMD
PCS
shows the LXT972A PHY protocol sublayers.
LXT97x PHY
Serializer /De-serializer
Link/Carrier Detect
Encoder /Decoder
De-scrambler
Scrambler/
100BASE-TX
MII Interface
5.7 100 Mbps Operation
B3395 -03
Table
Page 38
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