PEB3264H-V1.4 Infineon Technologies, PEB3264H-V1.4 Datasheet
PEB3264H-V1.4
Specifications of PEB3264H-V1.4
Related parts for PEB3264H-V1.4
PEB3264H-V1.4 Summary of contents
Page 1
...
Page 2
... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
Page 3
...
Page 4
... OLDU Page 367 Chapter 8 "Application Circuits" completely overworked. For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com. 2000-07-14 Data Sheet DS1 "Functional Overview" completely updated. ...
Page 5
... Receive Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.4.3 Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.5 Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.5.1 Ringer Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.5.2 Ring Trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.5.3 Ringing Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.5.4 DuSLIC Ringing Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.5.5 Internal Balanced Ringing via SLICs . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.5.6 Internal Unbalanced Ringing with SLIC 3.5.7 External Unbalanced Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.6 Signaling (Supervision 3.7 Metering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.7.1 Metering by 12/16 kHz Sinusoidal Bursts ...
Page 6
... SLIC Power Consumption Calculation in Ringing Mode . . . . . . . . . 103 4.8 Integrated Test and Diagnosis Functions (ITDF 107 4.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 4.8.1.1 Conventional Line Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 4.8.1.2 DuSLIC Line Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 4.8.2 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.8.2.1 Line Test Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.8.2.2 Integrated Signal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.8.2.3 Result Register Data Format ...
Page 7
... Foreign- and Ring Voltage Measurements . . . . . . . . . . . . . . . . . . . 129 4.9 Signal Path and Test Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 4.9.1 Test Loops DuSLIC-E/-E2/- 132 4.9.2 Test Loops DuSLIC-S/- 134 4.10 Caller ID Buffer Handling of SLICOFI 137 5 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 5.1 PCM Interface with a Serial Microcontroller Interface . . . . . . . . . . . . . . . 138 5.1.1 PCM Interface ...
Page 8
... Power Dissipation PEB 3265 (SLICOFI- 340 7.4.4 Power Dissipation PEB 3264, PEB 3264-2 (SLICOFI-2S/-2S2 341 7.4.5 Power Up Sequence for Supply Voltages . . . . . . . . . . . . . . . . . . . . . . 341 7.4.6 Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 7.5 AC Transmission DuSLIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 7.5.1 Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 7.5.2 Gain Tracking (Receive or Transmit 352 7.5.3 Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 7.5.4 Out-of-Band Signals at Analog Output (Receive) ...
Page 9
... Internal Ringing (Balanced/Unbalanced 367 8.1.1 Circuit Diagram Internal Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 8.1.2 Protection Circuit for SLIC-E/-E2 and SLIC 369 8.1.3 Protection Circuit for SLIC 370 8.1.4 Bill of Materials (Including Protection 371 8.2 External Unbalanced Ringing with DuSLIC-E/-E2/-S/-S2/- 372 8.3 DuSLIC Layout Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 9 Package Outlines ...
Page 10
... Balanced Ringing via SLIC-E/-E2, SLIC-S and SLIC Figure 28 Unbalanced Ringing Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 29 Teletax Injection and Metering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 30 Soft Reversal (Example for Open Loop Figure 31 DuSLIC AC Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 32 DuSLIC EDSP Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 33 Bellcore On-hook Caller ID Physical Layer Transmission . . . . . . . . . . 68 Figure 34 Line Echo Cancelling Unit - Block Diagram . . . . . . . . . . . . . . . . . . . . . 69 Figure 35 UTD Functional Block Diagram ...
Page 11
... Foreign Voltage Measurement Principle . . . . . . . . . . . . . . . . . . . . . . 130 Figure 53 AC Test Loops DuSLIC-E/-E2/- 132 Figure 54 DC Test Loops DuSLIC-E/-E2/- 133 Figure 55 AC Test Loops DuSLIC 134 Figure 56 AC Test Loops DuSLIC- 135 Figure 57 DC Test Loops DuSLIC-S/- 136 Figure 58 General PCM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Figure 59 Setting of Slopes in Register PCMC1 ...
Page 12
... Figure 100 Application Circuit, External Unbalanced Ringing . . . . . . . . . . . . . . . 372 Figure 101 Application Circuit, External Unbalanced Ringing for Long Loops 373 Figure 102 DuSLIC Layout Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 Figure 103 PEB426x (SLIC-S/-S2, SLIC-E/-E2, SLIC-P 376 Figure 104 PEB 3264, PEB 3264-2, PEB 3265 (SLICOFI-2x 377 ...
Page 13
... Table 36 Measurement Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Table 37 SLICOFI-2x PCM Interface Configuration . . . . . . . . . . . . . . . . . . . . . 140 Table 38 Active PCM Channel Configuration Bits . . . . . . . . . . . . . . . . . . . . . . 142 Table 39 IOM-2 Time Slot Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Table 40 SLIC-S/-S2 Interface Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Table 41 SLIC-S/-S2 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Table 42 SLIC-E/-E2 Interface Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Data Sheet TRANS T ...
Page 14
... List of Tables Table 43 SLIC-E/-E2 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Table 44 SLIC-P Interface Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Table 45 SLIC-P Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Table 46 SLIC-P Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Table 47 M2, M1, M0: General Operating Mode . . . . . . . . . . . . . . . . . . . . . . . 164 Table 48 Valid DTMF Keys (Bit DTMF-KEY4 = 178 Table 49 DTMF Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Table 50 Typical Usage for the three Ring Offsets . . . . . . . . . . . . . . . . . . . . . . 208 Table 51 CRAM Coefficients ...
Page 15
... Preliminary Preface This document describes the DuSLIC chip set comprising a programmable dual channel SLICOFI-2x codec and two single channel high-voltage SLIC chips. For more DuSLIC related documents please see our webpage at http://www.infineon.com/duslic. To simplify matters, the following synonyms are used: SLICOFI-2x: ...
Page 16
... Overview DuSLIC is a chip set, comprising one dual channel SLICOFI-2x codec and two single channel SLIC chips highly flexible codec/SLIC solution for an analog line circuit and is widely programmable via software. Users can now serve different markets with a single hardware design that meets all different standards worldwide. ...
Page 17
... The SLIC-E, SLIC-E2 and SLIC-P devices are manufactured in Infineon Technologies robust and well proven 170 V Smart Power technology. The SLIC-S and SLIC-S2 devices are manufactured in Infineon Technologies 90 V Smart Power technology and offer further cost reduction. Usage of Codec´s and SLIC´s: ...
Page 18
... Overload protection Battery switching Ring amplification On-hook transmission Polarity reversal Figure 1 DuSLIC Chip Set Data Sheet SLICOFI-2x LV SLIC Functions Codec Filter Functions Programmable DC feeding Filtering Ring generation PCM compression/expansion Supervision Programmable gain Teletax generation Programmable frequency Teletax notch filter Impedance matching ...
Page 19
... Dual Channel Subscriber Line Interface Circuit DuSLIC Version 1.2 1.1 Features • Internal unbalanced/balanced ringing capability Vrms • Programmable Teletax (TTX) generation • Programmable battery feeding with capability for driving longer loops • Fully programmable dual-channel codec • Ground/loop start signaling • ...
Page 20
... Preliminary 1.2 Logic Symbols Tip/Ring interface Power supply Figure 2 Logic Symbol SLIC-S / SLIC-S2 / SLIC-E / SLIC-E2 Tip/Ring interface Power supply Figure 3 Logic Symbol SLIC-P Data Sheet TIP RING PEB 4264 PEB 4264-2 PEB 4265 VDD PEB 4265-2 AGND VHR BGND VBATL VBATH ...
Page 21
... C1A C1B Logic C2A control C2B IO1A IO2A IO3A I/O IO4A feeding IO1B IO2B IO3B IO4B Figure 4 Logic Symbol SLICOFI-2/-2S/-2S2 Data Sheet PCM/IOM-2 TS1/DCLK SEL24/DRA DCL/PCLK PEB 3265 PEB 3264 PEB 3264-2 21 DuSLIC Overview INT TS0/DIN TS2/CS IOM-2 interface DU/DOUT µ ...
Page 22
... Digital Loop Carrier (DLC) • Wireless Local Loop • Fiber in the Loop • Private Branch Exchange • Intelligent NT (Network Termination) for ISDN • ISDN Terminal Adapter • Central Office • Cable Modem • XDSL NT • Router Data Sheet 22 DuSLIC Overview 2000-07-14 ...
Page 23
... Figure 5 Pin Configuration SLIC-S/-S2, SLIC-E/-E2, SLIC-P (top view) Note: The SLIC is only available in a P-DSO-20-5 package with heatsink on top. Please note that the pin counting for the P-DSO-20-5 package is clockwise (top view) in contrast to similar type packages which mostly count counterclockwise. Data Sheet ...
Page 24
... Preliminary Table 2 Pin Definitions and Functions SLIC-S/-S2 and SLIC-E/-E2 Pin Symbol Input (I) No. Output (O) 1 RING I/O 2 TIP I/O 3 BGND Power 4 VHR Power 5 VDD Power 6 VBATL Power 7 VBATH Power 8 N.C. – 9 AGND Power 10 CEXT O 11 VCMS I 12, ACN ACP 14, DCN I 15 ...
Page 25
... Note: The SLIC is only available in a P-DSO-20-5 package with heatsink on top. Please note that the pin counting for the P-DSO-20-5 package is clockwise (top view) in contrast to similar type packages which mostly count counterclockwise. Data Sheet Function Current output: longitudinal line current scaled down by a ...
Page 26
... Preliminary Table 3 Pin Definitions and Functions SLIC-P Pin Symbol Input (I) No. Output (O) 1 RING I/O 2 TIP I/O 3 BGND Power 4 N.C. – 5 VDD Power 6 VBATL Power 7 VBATH Power 8 VBATR Power 9 AGND Power 10 CEXT O 11 VCMS I 12, ACN ACP 14, DCN DCP I/O Data Sheet ...
Page 27
... Note: The SLIC is only available in a P-DSO-20-5 package with heatsink on top. Please note that the pin counting for the P-DSO-20-5 package is clockwise (top view) in contrast to similar type packages which mostly count counterclockwise. Data Sheet Function Current output: longitudinal line current scaled down by a ...
Page 28
... ILA ITACA ITA VCMITA VDDR GNDR VCMS VCM CREF SELCLK VCMITB ITB ITACB ILB C1B 1 Figure 6 Pin Configuration SLICOFI-2/-2S/-2S2 (top view) Data Sheet PEB 3265 PEB 3264 PEB 3264-2 28 DuSLIC Pin Descriptions 33 PCM/IOM-2 VDDPLL GNDPLL TCB DXB DXA TCA VDDD ...
Page 29
... INT O Data Sheet Function Ternary logic output for controlling the SLIC operation mode (channel B) Two-wire output voltage (DCP) (channel B) External capacitance for filtering (channel B) External capacitance for filtering (channel B) Two-wire output voltage (DCN) (channel B) Differential two-wire AC output voltage controlling the RING ...
Page 30
... Preliminary Table 4 Pin Definitions and Functions SLICOFI-2/-2S/-2S2 (cont’d) Pin Symbol Input (I) No. Output ( DOUT O 19 DCL I PCLK DRB I 21 SEL24 I DRA I 22 MCLK I 23 FSC I 24 GNDD Power 25 VDDD Power 26 TCA O 27 DXA O 28 DXB O 29 TCB O 30 GNDPLL Power ...
Page 31
... Two-wire output voltage (DCP) (channel A) Ternary logic output for controlling the SLIC operation mode (channel A) Ternary logic output, controlling the SLIC operation mode (channel A); indicating thermal overload of SLIC if a current of typically 150 A is drawn out Longitudinal current input (channel A) Transversal current input (AC) (channel A) ...
Page 32
... ITACB I 63 ILB I 64 C1B I SLIC-P is selected, IO2 cannot be controlled by the user, but is utilized by the SLICOFI-2 to control the C3 pin of SLIC-P. Data Sheet Function Transversal current input (AC + DC) (channel A) Reference pin for trans./long. current sensing (channel A) + 3.3 V analog supply voltage (bias) ...
Page 33
... Signaling (supervision) • Coding • Hybrid for 2/4-wire conversion • Testing An important feature of the DuSLIC design is the fact that all the SLIC and codec functions are programmable via the IOM-2 or PCM/µC-interface of the dual channel SLICOFI-2x device: • DC (battery) feed characteristics • ...
Page 34
... Caller ID modulator complies with all requirements of ITU-T recommendation V.23 and Bell 202. • LEC (Line Echo Cancellation) DuSLIC contains an adaptive line echo cancellation unit for the cancellation of near end echos ( cancelable echo delay time). • UTD (Universal Tone Detection) DuSLIC has an integrated Universal Tone Detection unit to detect special tones in the receive or transmit path (e ...
Page 35
... Current Sensor & Offhook Detection TIP Gain SLIC-S/-S2 RING V /V Control BAT H switch Logic * not available with SLICOFI-2S2 Figure 7 Line Circuit Functions included in the DuSLIC-S/-S2 SLIC-E/-E2/-P Current Sensor & Offhook Detection TIP Gain RING V /V Control BAT H switch Logic SLIC-E/-E2/-P Current Sensor & ...
Page 36
... Preliminary 3.2 Block Diagrams Figure 9, Figure 10 and SLIC versions of the DuSLIC chip set. BGND PDRHL PDRH I TO TIP RING PDRHL PDRH VBATL VBATH (Sub) Figure 9 Block Diagram SLIC-S/-S2 (PEB 4264/-2) Data Sheet Figure 11 show the basic functional blocks and circuits for all ...
Page 37
... Preliminary BGND PDRHL PDRH I TO TIP RING PDRHL PDRH VBATL VBATH (Sub) Figure 10 Block Diagram SLIC-E/-E2 (PEB 4265/-2) Data Sheet PEB 4265/- Off hook ( 100 R T Current ( 200 Sensor R T 60k 5k VHI I T VBI SymFi VHI I R 60k VBAT BIAS Switch ...
Page 38
... Preliminary PDRR PDRRL PDRH PDRHL TIP RING PDRR PDRRL VBATL VBATH VBATR (SUB) Figure 11 Block Diagram SLIC-P (PEB 4266) Data Sheet PEB 4266 ( Off-hook BGND ( 100 R T Current ( 200 sensor 60k BGND VBI SymFi I R 60k PDRH PDRHL Battery BIAS switch ...
Page 39
... Preliminary Figure 12 shows the internal block structure of all SLICOFI-2x codec versions available. The Enhanced Digital Signal Processor (EDSP) realizing the add-on funtions integrated in the SLICOFI-2 (PEB 3265) device. PEB 3265 / PEB 3264 / PEB 3264-2 CDCNB CDCPB CDCNA CDCPA Super- ILA vision ...
Page 40
... Preliminary 3.3 DC Feeding DC feeding with the DuSLIC is fully programmable by using the software coefficients depicted in Table 5 on Page Figure 13 shows the signal paths for DC feeding between the SLIC and SLICOFI-2x: TIP SLIC Channel A RING DCP DCN ACP ACN TIP SLIC RING Channel B ...
Page 41
... The DuSLIC DC feeding characteristic has three different zones: the constant current zone, the resistive zone and the constant voltage zone. A voltage reserve V Chapter 3.3.7) can be selected to avoid clipping the high level AC signals (e.g. TTX) and to take into account the voltage drop of the SLIC. The DC feeding characteristic is shown in Figure 14. ...
Page 42
... In the off-hook state, the feed current must usually be kept at a constant value independent of load (see information to SLICOFI-2x via the IT pin (input pin for DC control). SLICOFI-2x compares the actual current with the programmed value and adjusts the SLIC drivers as I necessary. in the constant current zone is programmable from TIP/RING depending on the used SLIC version ...
Page 43
... The operating point in this case crosses from the constant current zone for low and medium impedance loops to the resistive zone for high impedance loops (see Figure 16). The resistance of the zone I TIP/RING Figure 16 Resistive Zone Data Sheet R of DuSLIC provides extra flexibility over a wide K12 R is programmable from K12 R LOAD R K12 V RES |V BAT 43 ...
Page 44
... Figure 17) is used in some applications to supply constant and the current depends TIP/RING R = PRE R seen at the RING and TIP wires of the K12 V RES V |V LIM BAT 44 DuSLIC Functional Description necessary for Stab Prot , R and V is given in K12 LIM R LOAD | V TIP/RING ezm14036.emf 2000-07-14 ...
Page 45
... R … 1000 K12 … LIM V > LIM K1 K1 Data Sheet K12 LIM Condition – only for DuSLIC-S, DuSLIC-E, DuSLIC-P only for DuSLIC-S2, DuSLIC-E2 only for DuSLIC-S, DuSLIC-E, DuSLIC-P only for DuSLIC-S2, DuSLIC-E2 – only ( , ) K12 and ( K12 – – R only ( K12 ...
Page 46
... Preliminary 3.3.6 SLIC Power Dissipation The major portion of the power dissipation in the SLIC can be estimated by the power dissipation in the output stages. The power dissipation can be calculated from – V SLIC BAT TIP/RING I TIP/RING I 0 Figure 19 Power Dissipation For further information see Data Sheet ...
Page 47
... V consists of: RES • Voltage reserve of the SLIC output buffers: this voltage drop depends on the output current through the Tip and Ring pins. For a standard output current of 25 mA, this voltage reserve is a few volts (see • Voltage reserve for AC speech signals: max. signal amplitude (example 2 V) • ...
Page 48
... K + K1,ACTR – K12,ACTR B K12 I,ACTR K2,ACTR K2 B K12 – K2,ACTR LIM,ACTR Data Sheet V (DuSLIC-P possible to supply the constant BATR shows the DC feeding impedances ACTR Extended Battery Feeding Mode R MAX R K12 LIM K1 K1, ACTR |V | BATH (DuSLICOS DC Control Parameter 1/ – K12 – ...
Page 49
... SLICOFI-2x uses either an IOM PCM digital interface. In receive direction, SLICOFI-2x converts PCM data from the network and outputs a differential analog signal (ACP and ACN) to the SLIC, that amplifies the signal and applies it to the subscriber line. In transmit direction, the transversal (IT) and longitudinal (IL) currents on the line are sensed by the SLIC and fed to the SLICOFI-2x ...
Page 50
... DSP. The digital data stream is up-sampled and converted to a corresponding analog signal. After smoothing by post-filters in the SLICOFI-2x, the AC signal is fed to the SLIC, where it is superimposed on the DC signal. The DC signal has been processed in a separate DC path. A TTX signal, generated digitally within SLICOFI-2x, can also be added ...
Page 51
... Impedance Matching The SLIC outputs the voice signal to the line (receive direction) and also senses the voice signal coming from the subscriber. The AC impedance of the SLIC and the load impedance need to be matched in order to maximize power transfer and minimize two- wire return loss. The two-wire return loss is a measure of the impedance matching between a transmission line and the AC termination of DuSLIC ...
Page 52
... Preliminary 3.5 Ringing With the 170 V technology used for the SLIC, a ringing voltage Vrms can be generated on-chip without the need for an external ringing generator. The SLICOFI-2x generates a sinusoidal ringing signal that causes less noise and cross-talk in neighboring lines than a trapezoidal ringing signal. The ringing frequency is programmable from 3 to 300 Hz ...
Page 53
... SLICOFI-2x. The threshold for the ring trip DC current is set internally in SLICOFI-2x, programmed via the digital interface. The DC offset for ring trip detection can be generated by the DuSLIC chip set and the internal ring trip function can be used, even if an external ringing generator is used. ...
Page 54
... In most applications 20 V will reduce the achievable maximum ringing voltage. For short loops 10 SLIC-S allows balanced ringing Vrms and is dedicated for short loop or PBX applications. For SLIC-S2 only external ringing is provided. SLIC-E/-E2 allows balanced ringing Vrms and can therefore be used in systems with higher loop impedance ...
Page 55
... SLICOFI-2x (see Figure • Activating the ringing mode by setting the CIDD/CIOP bits M2, M1 101. • Setting the DuSLIC internal ring frequency to a value according a factor of about 0.75 of the external ring frequency. The ring relay is controlled by the IO1 pin (see capability of the IO1 ouput, no additional relay driver is necessary. ...
Page 56
... Preliminary E xte lta Figure 26 External Ringing Zero Crossing Synchronization Data Sheet DuSLIC Functional Description duslic_0015_zero_crossing.emf 2000-07-14 ...
Page 57
... V RT,RMS load the rms voltage measured directly at pins RING and TIP at the SLIC output without any ringer RT0,RMS load. For calculation of the ringing voltage at the ringer load see the Voltage and Power Application Note and the accompanying MS Excel Sheet for calculation. ...
Page 58
... RING,RMS When the called subscriber goes off-hook path is established from the Ring to the Tip line. The DC current is recognized by the SLICOFI-2 because it monitors the IT pin. An interrupt indicates ring trip if the line current exceeds the programmed threshold. The same hardware can be used for integrated balanced or unbalanced ringing. The balanced or unbalanced modes are configured by software ...
Page 59
... BCR2. A synchronization signal of the external ringer is applied to the SLICOFI-2x via the RSYNC pin. The external relay is switched on or off synchronously to this signal via the IO1 pin of the SLICOFI-2x according to the actual mode of the DuSLIC. An interrupt is generated if the DC current exceeds the programmed ring trip threshold ...
Page 60
... In this mode, the Tip wire is switched to high impedance mode. Ring ground detection is performed by the internal current sensor in the SLIC and transferred to the SLICOFI-2x via the IT pin. Ground Key Detection The scaled longitudinal current information is transferred from the SLIC via the IL pin and R the external resistor to SLICOFI-2x. This voltage is compared with a fixed threshold ...
Page 61
... To satisfy worldwide application requirements, SLICOFI-2/-2S metering injection of either kHz signals with programmable amplitudes. SLICOFI-2/-2S also has an integrated adaptive TTX notch filter and can switch the TTX signal to the line in a smooth way. When switching the signal to the line, the switching noise is less than 1 mV. ...
Page 62
... Preliminary 3.7.2 Metering by Polarity Reversal SLICOFI-2/-2S also supports metering by polarity reversal by changing the actual polarity of the voltages on the TIP/RING lines. Polarity reversal is activated by switching the REVPOL bit in register BCR1 to one or switching to the “Active with Metering” mode by the CIDD or CIOP command (see Page 78) ...
Page 63
... For the MIPS requirements of the different EDSP algorithms see Figure 31 shows the AC signal path for DuSLIC with the ADCs and DACs, impedance matching loop, trans-hybrid filter, gain stages and the connection to the EDSP. VIN ...
Page 64
... In all SLICOFI-2x codec versions the 16 standard DTMF tone pairs can be generated independently in each channel via two integrated tone generators. Alternatively the frequency and the amplitude of the tone generators can be programmed individually via the digital interface ...
Page 65
... Level in frequency range 30 Hz … 480 Hz level of DTMF frequency + 22 dB Error rate better than 1 in 10000 Error rate better than 14 in 10000 65 DuSLIC Notes Programmable – Programmable Programmable Related to center frequency Related to center frequency dB referenced to lowest amplitude tone – ...
Page 66
... Caller ID Generation (only DuSLIC-E/-E2/-P) A generator to send calling line identification (Caller ID, CID) is integrated in the DuSLIC chip set. Caller generic name for the service provided by telephone utilities that supply information like the telephone number or the name of the calling party to the called subscriber at the start of a call ...
Page 67
... SLICOFI-2 interrupt signal. Caller data is transferred from the buffer via the interface pins to the SLIC-E/-E2/-P and fed to the Tip and Ring wires. The Caller ID data bytes from CID-data buffer are sent LSB first. ...
Page 68
... G: 1 second ring burst Figure 33 Bellcore On-hook Caller ID Physical Layer Transmission Data Sheet Mark Data Packet Parameter Message Parameter Body More Parameter Parameter Parameter Length Byte Bytes Message Body Message 68 DuSLIC Functional Description Second Ring Burst F G More Parameter Checksum Messages ezm14014.wmf 2000-07-14 ...
Page 69
... Line Echo Cancelling (LEC) (only DuSLIC-E/-E2/-P) The DuSLIC contains an adaptive line echo cancellation unit for the cancellation of near end echoes. With the adaptive balancing of the LEC unit the Transhybrid Loss can be improved value of about 50 dB. The maximum echo cancellation time selectable ...
Page 70
... Universal Tone Detection (UTD) (only DuSLIC-E/-E2/-P) Each channel of the DuSLIC has two Universal Tone Detection units which can be used to detect special tones in the receive and transmit paths, especially fax or modem tones (e.g., see the modem startup sequence described in recommendation ITU-T V.8). ...
Page 71
... If the bandwidth parameter is programmed to a negative value, the UTD unit can be used for the detection of silence intervals in the whole frequency range. The DuSLIC UTD unit is compatible with ITU-T G.164. The UTD is resistant to a modulation with 15 Hz sinusoidal signals and a phase reversal but is not able to detect the 15 Hz modulation and the phase reversal ...
Page 72
... The glow lamp circuit also requires a resistor (R phone. When activated, the lamp must be able to either blink or remain on constantly. In non-DuSLIC solutions the telephone ringer may respond briefly if the signal slope is too steep, which is not desirable. DuSLIC’s integrated ramp generator can be programmed to increase the voltage slowly, to ensure activating the lamp and not the ringer ...
Page 73
... Preliminary To activate the Message Waiting function of DuSLIC the following steps should be performed: • Activating Ring Pause mode by setting the M0-M2 bits • Select Ring Offset RO2 by setting the bits in register LMCR3 • Enable the ramp generator by setting bit RAMP-EN in register LMCR2 • ...
Page 74
... Preliminary 3.10 Three-party Conferencing (only DuSLIC-E/-E2/-P) Each DuSLIC channel has a three-party conferencing facility implemented which consist of four PCM registers, adders and gain stages in the microprogram and the corresponding control registers (see This facility is available in PCM/ C mode only. The PCM control registers PCMR1 ...
Page 75
... X1 are in use, and voice data are transferred from subscriber A to analog subscriber S and vice versa. • External Conference In this mode the SLICOFI-2 acts as a server for a three-party conference of subscribers B, C and D which may be controlled by any device connected to the PCM highways. The SLICOFI-2 channel itself can remain in power down mode to lower power consumption. • ...
Page 76
... Data Sheet S-HB S-LB depends on – DS2 – DS1 DS1- DS2- DS2- DS1 DuSLIC Functional Description 1) Transmit PCM Channels 3) X1 X1L X2 X3 – depends on conference mode conference mode – – DS2 – DS1- DS2 2000-07-14 X4 – DS2- LB ...
Page 77
... LIN16 Mode Like the PCM16 mode for 16 kHz sample rate but for linear data. Channels (X1 to X4) are used for receiving (transmitting) the high and low bytes of the two linear data samples DS1 and DS2. Data Sheet Functional Description 77 DuSLIC 2000-07-14 ...
Page 78
... Preliminary 4 Operational Description 4.1 Operating Modes for the DuSLIC Chip Set Table 12 Overview of DuSLIC Operating Modes SLICOFI-2x Mode SLIC-S/ SLIC-S2 Sleep (SL) – Power Down PDRH Resistive (PDR) Power Down PDH High Impedance (PDH) Active High ACTH (ACTH) Active Low ACTL (ACTL) ...
Page 79
... No special wake-up is needed if only one channel is in sleep mode. A simple mode change ends the sleep mode. • A sleeping SLICOFI-2 is woken up if the CS pin is drawn to low level when the PCM/ C interface is used or the MX bit is set to zero when the IOM-2 interface is used. Note that no programming is possible until the SLICOFI-2 wakes up ...
Page 80
... The Ring on Tip (ROT) mode is the equivalent to the ROR mode. Active with HIT This is a testing mode where the Tip wire is set to a high impedance mode used for special line testing only available in an active mode of the SLICOFI-2x to enable all necessary test features. Data Sheet V (bit ACTL = 1) ...
Page 81
... The Tip wire is set to high impedance in Ground Start mode. Any current drawn on the Ring wire leads to a signal on IT, indicating off-hook. Ring Pause The Ring burst is switched off in Ring Pause, but the SLIC remains in the specified mode and the off-hook recognition behaves like in ringing mode (Ring Trip). Data Sheet ...
Page 82
... Preliminary 4.2 Operating Modes for the DuSLIC-S/-S2 Chip Set Table 13 DuSLIC-S/-S2 Operating SLICOFI-2S / SLIC-S / SLICOFI-2S2 SLIC-S2 Mode Mode PDH PDH Power Down PDRH Resistive – PDRHL 1) Active Low ACTL (ACTL) Active High ACTH (ACTH) Active Ring ACTR (ACTR) Ringing ACTR (Ring) ...
Page 83
... Preliminary Table 13 DuSLIC-S/-S2 Operating SLICOFI-2S / SLIC-S / SLICOFI-2S2 SLIC-S2 Mode Mode Ring Pause ACTR Active with HIR HIR Active with HIT HIT 1) load ext. C for switching from PDRH to ACTH in on-hook mode V … Tip/Ring AC Voltage AC V … Tip/Ring DC Voltage DC Data Sheet Modes (cont’d) ...
Page 84
... Preliminary 4.3 Operating Modes for the DuSLIC-E/-E2 Chip Set Table 14 DuSLIC-E/-E2 Operating SLICOFI-2 SLIC-E / SLIC-E/-E2 Mode SLIC-E2 Internal Mode Supply Voltages (+/–) [ PDH PDH Open/ Sleep PDRH Open/ Power PDRH Open/ Down Resistive 1) – PDRHL Open/ V Active Low ACTL BGND (ACTL) ...
Page 85
... Preliminary Table 14 DuSLIC-E/-E2 Operating SLICOFI-2 SLIC-E / SLIC-E/-E2 Mode SLIC-E2 Internal Mode Supply Voltages (+/–) [ Ringing ACTR V HR (Ring) V Ring ACTR HR Pause HIRT HIRT V HR Active with HIR V HR HIR Active with HIT V HR HIT 1) load ext. C for switching from PDRH to ACTH in on-hook mode V … ...
Page 86
... Preliminary 4.4 Operating Modes for the DuSLIC-P Chip Set Table 15 DuSLIC P Operating SLICOFI-2 SLIC-P SLIC-P Mode Mode Internal Supply Voltages PDH PDH V BATR Sleep PDRH V BATH Sleep PDRR V BATR V Power PDRH BATH Down Resistive 1) V – PDRHL BATH V – PDRR BATR ...
Page 87
... Preliminary Table 15 DuSLIC P Operating SLICOFI-2 SLIC-P SLIC-P Mode Mode Internal Supply Voltages Active ACTR V BATR Ring (ACTR) V Ringing ACTR BATR (Ring) Ringing ROR V BATR (Ring) Ringing ROT V BATR (Ring) Ring ACTR, V BATR Pause ROR, ROT V HIRT HIRT BATR V Active with HIR ...
Page 88
... Reset Mode and Reset Behavior 4.5.1 Hardware and Power On Reset A reset of the DuSLIC is initiated by a power-on reset or a hardware reset by setting the signal at RESET input pin to low level for at least 4 µs rejection which will safely suppress spikes with an duration of less than 1 µs By setting the reset signal to low, the chip will be reset (see • ...
Page 89
... Preliminary sig µ all I ctiva all tive ( intern sto intern a l clo cks d e activa igh Figure 39 DuSLIC Reset Sequence Data Sheet I tin µ duslic_0016_reset_sequence.emf 89 DuSLIC Operational Description t F irs FI sible 2000-07-14 ...
Page 90
... Preliminary 4.5.2 Software Reset When performing a software reset, the DuSLIC is running the reset routine and sets the default settings of the configuration registers. The software reset can be performed individually for each channel. Table 16 Default Values – 100 K12 f 25.4 Hz RING A 62 Vrms ...
Page 91
... Approximately 900 real input impedance Approximately BRD impedance for balanced network Relative level in transmit Relative level in receive Teletax generator amplitude at the resistance of 200 Teletax generator frequency Tone generator 1 (– 12 dBm) Tone generator 2 (– 10 dBm) AC level meter band pass 91 DuSLIC Operational Description 2000-07-14 ...
Page 92
... Any change (at some bits only transitions from one of the four interrupt registers leads to an interrupt. The interrupt channel bit INT-CH in INTREG1 is set to one and all interrupt registers of one DuSLIC channel are locked at the end of the interrupt procedure (500 µs period). Therefore all changes within one 2 kHz frame are stored in the interrupt registers ...
Page 93
... Both AC and DC loops are inactive. To achieve the lowest power consumption of the DuSLIC chip set, the clock cycles fed to the MCLK and PCLK pins have to be shut off. For changing into another state the DuSLIC has to be woken up according to the procedure described in Chapter – ...
Page 94
... Preliminary – Ringing For SLIC-E/-E2 and SLIC-S, an auxiliary positive supply voltage total supply range 150 V. For SLIC-P the whole supply range is provided The low-impedance line feed ( BATR 101 output impedance) with a balanced sinusoidal Ring signal Vrms, plus a DC offset sufficient to supply very long lines at any kind of ringer load and to reliable detect Ring trip ...
Page 95
... In Power Down modes, the internal bias currents are reduced to a minimum and no current is fed to the line (see hook detection, the power dissipation for SLIC-P) is negligible. Note that this is the dominant factor for a low mean power value in large systems large percentage of lines are always inactive. ...
Page 96
... V ) whenever line resistance is small enough. This method is BATL supported on the SLIC-E/-E2 by integrating a battery switch. With a standard battery voltage of – long lines can be driven line current. The SLIC-P PEB 4266 “low-power” version even allows three battery voltages (typically the most negative one, e.g. – used in Active mode (On-hook) and Power Down mode) ...
Page 97
... ACTH 222 ACTR 379 1) The formulas for the calculation of the power shares Figure 41 shows the total power dissipation (ACTH and ACTL) with switched battery voltage ( The power dissipation in the SLIC is strongly reduced for short lines. Data Sheet Line Currents TRANS TRANS ...
Page 98
... Figure 41 SLIC-E/-E2 Power Dissipation with Switched Battery Voltage Typical Power Consumption Calculation with SLIC-P (Internal Ringing) Assuming a typical application where the following battery voltages are used – BATL R guaranteed 1200 L V Requirement for TTX: ...
Page 99
... ACTL 81.7 ACTH 135 ACTR (Extended 383 Battery Feeding) ROR, ROT 263 (Ring Pause) Figure 43 shows the total power dissipation PTOT of the SLIC-P in Active mode (ACTH and ACTL) with switched battery voltage ( 700 600 500 400 300 200 100 0 Figure 42 SLIC-P Power Dissipation (Switched Battery Voltage, Long Loops) ...
Page 100
... Preliminary Typical Power Consumption Calculation with SLIC-P (External Ringing) Assuming a typical application where the following battery voltages are used – BATL R teed 600 . L Requirement for TTX: V TTX,rms This is a typical lowest-power application, where V V and and is used in the active modes with battery switching. ...
Page 101
... Figure 43 SLIC-P Power Dissipation (Switched Battery Voltage, Short Loops) 4.7.3.4 Ringing Modes Internal Balanced Ringing (SLIC-E/-E2 and SLIC-P) The SLIC-E/-E2/-P internal balanced ringing facility requires a higher supply voltage V (auxiliary voltage ). The highest share of the total power is dissipated in the output HR stage of the SLIC-E/-E2/-P. The output stage power dissipation ...
Page 102
... BATR DROP External Ringing (SLIC-E/-E2 and SLIC-P) When an external ring generator and ring relays are used, the SLIC can be switched to Power Down mode. The “low-power” SLIC-P is optimized for extremely power-sensitive applications (see Table 23). SLIC-P has three different battery voltages. ...
Page 103
... Preliminary 4.7.3.5 SLIC Power Consumption Calculation in Ringing Mode The average power consumption for a ringing cadence of 1 second on and 4 seconds off is given TOT, average TOT, Ringing with k = 0.20 The typical circuit for ringing is shown in Circuit Diagram for Ringing i R RNG Z RNG C RNG ...
Page 104
... Preliminary – Power Consumption Calculation for SLIC-E/-E2 in Balanced Ringing Mode With the example of the above calculation for SLIC-E/-E2 (see typical ringer load 450 = 3.4 F, required ringing voltage RNG RNG frequency Hz. DC Offset Voltage for ring trip detection RNG Table 24 shows the power calculation for the total power dissipation ...
Page 105
... Preliminary – Power Consumption Calculation for SLIC-P in Balanced Ringing Mode With the example of the above calculation with Chapter 4.7.3.3) when the internal ringing feature will be used. R Typical ringer load Vrms and ringing frequency RNGr V detection = Table 25 shows the power calculation for the total power dissipation ...
Page 106
... Preliminary – Power Consumption Calculation for SLIC-P in Unbalanced Ringing Mode A similar power calculation is valid for internal unbalanced ringing mode, which is only available for the SLIC-P. With the following example – BATL guaran-teed up to 600 . R Typical ringer load Vrms and ringing frequency ...
Page 107
... DuSLIC. With the DuSLIC both channels are able to perform line tests concurrently, which also has a tremendous impact on the test time. All in all, the DuSLIC increases the quality of service and reduces the costs in various applications. ...
Page 108
... The two-channel chip set has a set of signal generators and features implemented to accomplish a variety of diagnostic functions. The SLICOFI-2 device generates all test signals, processes the information that comes back from the SLIC-E/-E2/-P and provides the data to a higher level master device, e.g. a microprocessor. All the tests can be initiated by the micropocessor and the results can be read back very easily ...
Page 109
... IMG. FILTER 109 Operational Description VOICE PATH a RECTIFIER INTEGRATOR SHIFT 1x16ms b FACTOR ... K 16x16ms INTAC CRAM LMCR3: LM-ITIME[3:0] c A-B PCM OUT: Transmit Data to PCM or IOM-2 Interface MUX LMCR1: LM2PCM RESULT REG MUX LMRES1/2 Programmable Not Programmable LMCR2: LM-SEL[3:0] duslic_0010_level_meter_block.emf DuSLIC 226. 2000-07-14 ...
Page 110
... Both AC and DC levelmeter allow to use a programmable integrator. The integrator may be configured to run continuously or single. Single Measurement Sequence (AC & DC Levelmeter Figure 46 Single Measurement Sequence (AC&DC Levelmeter) Data Sheet Positive Value Range + Fullscale 0 0x7FFF 0 + 32767 rio d Read Result LMRES1/2 110 DuSLIC Operational Description S tart asurem ent rio d duslic_0019_LM_single.emf 2000-07-14 ...
Page 111
... Continuous Measurement Sequence (AC Levelmeter) Data Sheet rio rio µ µ s Read Result LMRES1 rio rio µ s Read Result LMRES1/2 111 Operational Description rio rio µ s Read Result Read Result LMRES1/2 LMRES1/2 duslic_0020_LM_contDC.emf rio µ µ s Read Result Read Result LMRES1/2 LMRES1/2 duslic_0021_LM_contAC.emf DuSLIC 2000-07-14 ...
Page 112
... The offset compensation value (see the offset registers OFR1 (bits OFFSET-H[7:0]) and OFR2 (bits OFFSET-L[7:0]) can be set to eliminate the offset caused by the SLIC-E/-E2/-P current sensor, pre-filter, and analog-to-digital converter. After the summation point the signal passes a programmable digital gain filter ...
Page 113
... Address 0x74: RGA1/RGF3 RGF1, RGF2 and RGF3 are 4 bit nibbles which control the ring frequency f RGA1 bit nibble which is calculated by DuSLICOS and controls the ringer amplitude (see DuSLICOS byte file). To ensure that RGA1 is not changed please perform a read/modify/write operation. Data Sheet ...
Page 114
... LM-VAL-H = "1001 1001" = 0x99 LM-VAL-L = "0110 0010" = 0x62 LM = 0x9962 = – 26270 Value LM = – 0.8017 Result Data Sheet f N RING Samples 500 4 250 7.81 256 3.91 512 bit two´s complement value of LM-VAL-H[7:0] and Table 31 is defined: : Result : Result 114 DuSLIC Operational Description 2000-07-14 ...
Page 115
... DC current on pin IT (bits LM-SEL[3:0] = 0101 current on pin IL (bits LM-SEL[3:0] = 1001) 3) Voltage on IO3 referenced Voltage on IO4 referenced Voltage on IO4 – IO3 referenced output voltage at SLIC measured via DCN – DCP (bits LM-SEL[3:0] = 0100) Data Sheet LM- (with Integrator PDR ------------------------- - V I TRANS AD R IT2 I 7 ...
Page 116
... DC regulation and the off-hook indication. In active mode you can freeze the output of the DC loop by setting the bit LM-HOLD to '1'. In ringburst mode it is possible that DuSLIC automatically switches back to ringpause mode because the measurement result was interpreted as off-hook. This can be avoided by programming the off-hook current to the maximum value (79 ...
Page 117
... CRAM: Address 0x34: CG1/LM-AC LM- bit nibble which contains K CG1 bit nibble which is calculated by DuSLICOS and controls the conference gain (see DuSLICOS byte file). To ensure that CG1 is not changed please perform a read/ modify/write operation. Data Sheet shows the path of the AC/TTX levelmeter functions. The AC INTAC ...
Page 118
... This is done by setting the following bits: Register BCR4: AR-DIS = 1, AX-DIS = 1, TH-DIS = 1, IM-DIS = 1, FRR-DIS = 1, FRX-DIS = 1 Register TSTR4: OPIM- OPIM- Register LMCR1: TEST- Data Sheet for the integrator is defined by: Samples ------------------------------------------------------------ - 2 K INT N Samples 118 Operational Description ö 3.14 + 2000-07-14 DuSLIC ...
Page 119
... IM-DIS = 1, FRR-DIS = 1, FRX-DIS = 1 Register TSTR4: OPIM- OPIM- Register LMCR1: TEST- The tone generator level is influenced by a factor K coefficients. The internal filter attenuation is 2.87 dB. – 2.87 --------------- - DAC Data Sheet 20 1 – 3.272 measured at SLIC INTAC Samples Trapez K ------------------- - = AC SLIC , 2 119 Operational Description LM Result = -------------------------------------------------- K N ...
Page 120
... Preliminary K Constant factor from Digital to Analog DA K Amplification factor of the SLIC AC,SLIC V Voltage at D/A converter refered to digital fullscale DAC Trapez Crestfactor of the trapazoidal signal Output voltage between Tip and Ring OUT DA TG The bytes below are valid for tone generator TG1 an a frequency of 1000 Hz. ...
Page 121
... LM-THRES in register INTREG 2 is set to '1 also possible to activate an interrupt when the LM-THRES bit changes by setting the bit LM-THM (levelmeter threshold mask bit) in register LMCR2 to '0'. The levelmeter threshold can be calculated with DuSLICOS or taken from CRAM: Address 0x32: LMTH2/LMTH1 ...
Page 122
... The current offset error can be measured with the DC levelmeter. The following settings are necessary to accomplish this: • The DuSLIC has to be set into the HIRT mode by setting the bits HIR and HIT in register BCR1 HIRT mode the line-drivers of the SLIC-E/-E2/-P are shut down and no resistors are switched to the line ...
Page 123
... Ring- and Tip line and measuring the DC loop current via IT pin. The following steps are necessary to accomplish this: • Program a certain ring offset voltage RO1, RO2, RO3 (see DuSLICOS DC Control Parameter 2/3). • Select ring offset voltage RNG-OFFSET[1:0] in register LMCR3 either to 01 11. ...
Page 124
... RNG-OFFSET[1:0] in register LMCR3 to 10. The exact value for the Ring offset voltage can be determined from the *.res result file generated by DuSLICOS during the calculation of the appropriate coefficients. • Select Active High (ACTH) mode by setting the line mode command CIDD/CIOP bits M2, M1 010 ...
Page 125
... Line Resistance Tip/GND and Ring/GND The DuSLIC offers the modes of setting either the Tip- or the Ring line to high impedance or even both by setting the bits HIR and HIT in register BCR1 accordingly. While one of both lines is set to high impedance, the other line is still active and able to supply a known voltage ...
Page 126
... Preliminary 4.8.2.11 Capacitance Measurements Capacitance measurements with the DuSLIC are accomplished by using the integrated ramp generator function. The ramp generator is capable of applying a voltage ramp to the Ring- and Tip line with the flexibility of: – Programmable slopes from 30 V/s to 2000 V/s – Programmable start- and stop DC voltage offsets via ring offsets – ...
Page 127
... Preliminary S LIC - Line C urrent Figure 51 Capacitance Measurement Data Sheet tart P rogram m able V oltage S lope S e ttlin g of lin e cu rre ring er de lay ctu al curre asu rem the settled cu rre RIN rio d 127 DuSLIC Operational Description S LIC - ezm14053.emf f 2000-07-14 ...
Page 128
... Symbol & Value dU/dt = 200 V 100 Hz RING T = 345 ms RING,DELAY RO1 = 70 V RO2 = – LM,DC = 1/100 RING 128 DuSLIC Operational Description = 9.8 µF = 6930 = OK DuSLICOS DC Control Parameter 3/3 DC Control Parameter 2/3 DC Control Parameter 2/3 DC Control Parameter 2/3 DC Control Parameter 2/3 DC Control Parameter 2/3 2000-07-14 ...
Page 129
... Foreign- and Ring Voltage Measurements The DuSLIC supports two user-programmable input/output pins (IO3, IO4) which can be used for measuring external voltages. If the pins IO3 and/or IO4 are led properly over a voltage divider to the Ring- and Tip wire, foreign voltages from external voltage sources supplied to the lines can be measured on either pin, even a differential measurement will be supported (IO4-IO3) ...
Page 130
... For that reason the voltage divider has to be referenced to VCM. The unknown foreign voltage V Data Sheet VCM PROT STAB SLIC-E/-E2/- PROT STAB R3 R4 VCM ± 1.0 V VCM 130 Operational Description IO4 IT IL SLICOFI-2 ACN / P DCN / P IO3 duslic_0009_foreign_voltage.emf – would result into VCM can be calculated as: FOREIGN DuSLIC 2000-07-14 ...
Page 131
... In case of measuring the ring voltage supplied to either Ring or Tip or even both (balanced ringing) pins via IO3 and IO4, the rectifier can be enabled by setting bit LM-RECT in register LMCR2 to 1. Data Sheet VCM R2 Table 31 0.5 V IOX,min --------------------- - + = VCM --------------------- - + = VCM R2 Figure 131 Operational Description 215 V – 212 V 45) by setting bit LM-EN in 2000-07-14 DuSLIC would ...
Page 132
... Preliminary 4.9 Signal Path and Test Loops The following figures show the main AC and DC signal path and the integrated analog and digital loops of DuSLIC-E/-E2/-P, DuSLIC-S and DuSLIC-S2. Please note the interconnections between the AC and DC pictures of the respective chip set. 4.9.1 ...
Page 133
... IO4 PREFI IO4 – IO3 VDD Offset PD-DCBUF PC-POFI-HI DCN/DCP DC BUF Programmable via CRAM Not Programmable Always available SWITCH Available only when bit SWITCH TEST- Figure 54 DC Test Loops DuSLIC-E/-E2/-P Data Sheet * : -L[7 :0] OFFSET* PD-DC- ADC DC-HOLD PD-DC-DA RAMP- RAMP ...
Page 134
... Preliminary 4.9.2 Test Loops DuSLIC-S/-S2 The AC test loops for DuSLIC-S since Teletax (TTX) is not available with SLICOFI-2S2. The DC test loops are identical. AC-DLB-32K COX16 a AX2 HPX2 HPX-DIS AX-DIS AR-DIS b AR2 COR-64 ITAC Adapt. Programmable via CRAM TTX-12K TTX-DIS Not Programmable SWITCH ...
Page 135
... AX2 HPX2 HPX-DIS AX-DIS AR-DIS b AR2 COR-64 Programmable via CRAM Not Programmable Always available SWITCH Available only when bit SWITCH TEST- Figure 56 AC Test Loops DuSLIC-S2 Data Sheet LPX FRX LPRX-CR FRX-DIS TH LPX-CR FRR-DIS LPR FRR TH-DIS PD-AC-PR PD-AC-GN PD-AC-AD AC-XGAIN ...
Page 136
... Preliminary PD-DC- PREFI PD-DCBUF PC-POFI-HI DCN/DCP DC BUF Programmable via CRAM Not Programmable Always available SWITCH Available only when bit SWITCH TEST- Figure 57 DC Test Loops DuSLIC-S/-S2 Data Sheet * OFFSET* PD-DC- ADC PD-DC- POFI DAC PD-OFHK IT OFFHOOK COMP PD-GNKC IL GNK COMP 136 ...
Page 137
... Preliminary 4.10 Caller ID Buffer Handling of SLICOFI-2 This chapter intends to describe the handling of the caller ID buffer and the corresponding handshake bits in the interrupt registers. Programming Sequence In order to send a caller ID information over the telephone line the following sequence should be programmed between the first and the second ring burst. The initialization part of the coefficients in the POP registers 43h to 4Ah must be done prior to that sequence ...
Page 138
... PCM Interface with a Serial Microcontroller Interface In PCM/ C interface mode, voice and control data are separated and handled by different pins of the SLICOFI-2x. Voice data are transferred via the PCM highways while control data are using the microcontroller interface. 5.1.1 PCM Interface The serial PCM interface is used to transfer A-law or -law-compressed voice data ...
Page 139
... The data rate of the interface can vary from 2*128 kbit/s to 2*8192 kbit/s (two highways). A frame may consist 128 time slots of 8 bits each. The time slot and PCM Data Sheet 125 µs High 'Z' Clock Voice Data Bit High 'Z' Voice Data 139 DuSLIC Interfaces 31 Time Slot High 'Z' High 'Z' ezm14046.wmf 2000-07-14 ...
Page 140
... Valid PCLK clock rates are Ordering No. B115-H6377-X-X-7600, published by Infineon Technologies. Data Sheet Time Slots [per highway 128 f/64 f/128 64 kHz (2 n 128) 140 DuSLIC Interfaces 1) User’s Data Rate [kbit/s per highway] ...
Page 141
... DBL NO- PCMC1: CLK SLOPE SLOPE DRIVE DBL NO- CLK SLOPE SLOPE DRIVE DBL NO- CLK SLOPE SLOPE DRIVE DBL NO- CLK SLOPE SLOPE DRIVE 141 DuSLIC Interfaces SHIFT PCMO[2: SHIFT PCMO[2: SHIFT PCMO[2: SHIFT PCMO[2: SHIFT PCMO[2: SHIFT PCMO[2: SHIFT PCMO[2: SHIFT PCMO[2: ezm22011.wmf ...
Page 142
... Preliminary 5.1.2 Control of the Active PCM Channels The SLICOFI-2x offers additional functionality on the PCM interface including three- party conferencing and a 16 kHz sample rate. Five configuration bits control, together with the PCM configuration registers, the activation of the PCM transmit channels. For ...
Page 143
... A write command consists of two command bytes and the following data bytes. The first command byte determines whether the command is read or write, how the command field used, and which DuSLIC channel ( written. The second command byte contains the address offset. A read command consists of two command bytes written to DIN. After the second command byte is applied to DIN, a dump-byte consisting of ‘ ...
Page 144
... In this case a data clock 1.024 MHz can be used on pin DCLK. Since the SLICOFI-2x will leave the basic reset routine only if clocks at the FSC, MCLK and PCLK pins are applied not possible to program the SLICOFI-2x without any clocks at these pins directly after the hardware reset or power on reset ...
Page 145
... TS0 DD DU TS0 Detail A DD Voice Channel A DU Voice Channel A Figure 62 IOM-2 Int. Timing for Voice Channels (Per 8-kHz Frame) 1) Available on request from Infineon Technologies. Data Sheet 125 µs TS1 TS2 TS3 TS1 TS2 TS3 Detail A Voice Channel B Monitor Channel Voice Channel B ...
Page 146
... The information is multiplexed into frames, which are transmitted at an 8-kHz rate. The frames are subdivided into 8 sub-frames, with one sub-frame dedicated to each transceiver or pair of codecs (in this case, two SLICOFI-2x channels). The sub-frames provide channels for data, programming and status information for a single transceiver or codec pair ...
Page 147
... DCL DD/DU Bit N Figure 64 IOM-2 Interface Timing (DCL = 2048 kHz, Per 8-kHz Frame) Both DuSLIC channels (see Set the IOM-2 time slot selection as shown in way channels can be handled with one IOM-2 interface on the line card. Table 39 IOM-2 Time Slot Assignment TS2 ...
Page 148
... For example: Data is placed onto the DD-Monitor-Channel by the monitor transmitter of the master device (DD-MX-Bit is activated, i.e., set to zero). This data transfer will be repeated within each frame (125 s rate) until it is acknowledged by the SLICOFI-2x monitor receiver by setting the DU-MR-bit to zero, which is checked by the monitor transmitter of the master device ...
Page 149
... MX bit and making a per-bit collision check on the transmitted monitor data (check if transmitted ‘1’s are on DU/DD line; DU/DD line are open-drain lines). Any abort leads to a reset of the SLICOFI-2x command stack, the device is ready to receive new commands. To maximum speed during data transfers the transmitter anticipates the falling edge of the receivers acknowledgment ...
Page 150
... ° RQT MR wait for MR ° RQT ack Figure 66 State Diagram of the SLICOFI-2x Monitor Transmitter MR … MR bit received on DD line MX … MX bit calculated and expected on DU line MXR … MX bit sampled on DU line CLS … Collision within the monitor data byte on DU line RQT … ...
Page 151
... MX ° LL valid new byte Figure 67 State Diagram of the SLICOFI-2x Monitor Receiver MR … MR bit calculated and transmitted on DU line MX … MX bit received data downstream (DD line) LL … Last lock of monitor byte received on DD line ABT … Abort indication to internal source Data Sheet ...
Page 152
... TIP/RING Interface The TIP/RING interface is the interface that connects the subscriber to the DuSLIC. It meets the ITU-T recommendation Q.552 for a Z interface and applicable LSSGR. For the performance of the TIP/RING interface see application circuits see Chapter Data Sheet 5 ...
Page 153
... Preliminary 5.4 SLICOFI-2S/-2S2 and SLIC-S/-S2 Interface The SLIC-S/-S2 PEB 4264/-2 operates in the following modes controlled by a ternary logic signal at the C1 and C2 input: Table 40 SLIC-S/-S2 Interface Code 1) C1 (Pin 18 “Overtemp” signaling possible via pin low. Table 41 SLIC-S/-S2 Modes SLIC Mode ...
Page 154
... Active modes. The Power Down mode PDRH is intended to reduce the power consumption of the linecard to a minimum: the SLIC-S/-S2 is switched off completely, no operation is available except off-hook detection. With respect to the output impedance of TIP and RING, two Power Down modes have ...
Page 155
... Sensor PDRHL PDRH VHI TIP I T VBI VHI RING PDRHL PDRH VBATL VBAT Switch VBATH VBI (Sub) Figure 68 Interface SLICOFI-2S/-2S2 and SLIC-S/-S2 Capacitor and resistor values are specified in Data Sheet PEB 4264/-2 VHI ( Switch ( 100 200 R T 60k - 10k S1 2k ...
Page 156
... Preliminary 5.5 SLICOFI-2 and SLIC-E/-E2 Interface The SLIC-E/-E2 PEB 4265/-2 operates in the following modes controlled by a ternary logic signal at the C1 and C2 input: Table 42 SLIC-E/-E2 Interface Code “Overtemp” signaling possible via pin low. Table 43 SLIC-E/-E2 Modes SLIC Mode Mode Description PDH ...
Page 157
... Active modes. The Power Down modes are intended to reduce the power consumption of the linecard to a minimum: the SLIC-E/-E2 is switched off completely, no operation is available. With respect to the output impedance of TIP and RING, three Power Down modes have to be distinguished: ...
Page 158
... PDRHL PDRH VHI TIP I T VBI VHI RING PDRHL PDRH VBATL VBAT Switch VBATH VBI (Sub) Figure 69 Interface SLICOFI-2 and SLIC-E/-E2 Capacitor and resistor values are specified in Data Sheet PEB 4265/-2 VHI ( Switch ( 100 R T Current ( 200 Sensor R T 60k - 10k ...
Page 159
... low pin of SLIC-P is typically connected to IO2 pin of SLICOFI-2. For extremely power-sensitive applications using external ringing the C3 pin can be connected to GND. In this case, SEL-SLIC[1:0] in register BCR1 has to be set to 10. Operating Modes for SLIC-P with Two Battery Voltages ( ...
Page 160
... The current through these resistors is sensed and transferred to the IT pin to allow off- hook supervision. PDRHL is used as a transition mode at a mode change from PDRH mode to ACTH mode (automatically initiated by SLICOFI mode change from PDRH to ACTH). Operating Modes for SLIC-P with Three Battery Voltages ( voice and External Ringing ...
Page 161
... PDRRL is used as a transition mode at a mode change from PDRR mode to ACTR mode (automatically initiated by SLICOFI mode change from PDRR to ACTR). High Impedance (HIR/HIT): In this mode each of the line outputs can be programmed to show high impedance. HIT switches off the TIP buffer, while the current through the RING output still can be measured ...
Page 162
... PDRR PDRRL PDRH PDRHL TIP I RING PDRR PDRH PDRRL PDRHL VBATL Battery VBATH switch VBATR (SUB) Figure 70 Interface SLICOFI-2 and SLIC-P Capacitor and resistor values are specified in Data Sheet PEB 4266 ( Off-hook ( 100 R T Current ( 200 sensor R T 60k BGND - 10k ...
Page 163
... Preliminary 6 SLICOFI-2x Command Structure and Programming With the commands described in this chapter, the SLICOFI-2x can be programmed, configured and tested very flexibly via the microcontroller interface or via the IOM-2 interface monitor channel. The command structure uses one and two-byte commands in order to ensure a high flexible and quick programming procedure for the most common commands ...
Page 164
... Channel address for the subsequent data ADR[2: ADR[2: (other codes reserved for future use) CMD[2:0] Command for programming the SLICOFI-2x ( command equivalent to the CIDD channel bits M[2:0] in microcontroller interface mode ( The first four commands have no second command byte following. All necessary information is present in the first command byte. ...
Page 165
... TEST-EN bit in register LMCR1 is set to 1 “N” – the register effects both SLICOFI-2x channels, “Y” – the register effects a specific SLICOFI-2x channel Detailed Name Test Register 1 165 ...
Page 166
... Overview of Commands SOP STATUS OPERATION Bit 7 6 Byte Byte 2 COP COEFFICIENT OPERATION Bit 7 6 Byte Byte 2 POP POP OPERATION (only SLICOFI-2 PEB 3265 used for DuSLIC-E/-E2/-P) Bit 7 6 Byte Byte 2 Data Sheet SLICOFI-2x Command Structure and Programming ADR[2:0] OFFSET[7: ADR[2:0] OFFSET[7:0] ...
Page 167
... SOP Command The SOP “Status Operation” command provides access to the configuration and status registers of the SLICOFI-2. Common registers change the mode of the entire SLICOFI-2 chip, all other registers are channel-specific possible to access single or multiple registers. Multiple register access is realized by an automatic offset increment. Write access to read-only registers is ignored and does not abort the command sequence ...
Page 168
... LMRES2 H 0F FUSE2 H 10 FUSE3 H 11 MASK H READY-M HOOK-M Data Sheet SLICOFI-2x Command Structure and Programming Interrupt Register 1 (read-only) GNDK GNKP ICON Interrupt Register 2 (read-only) RSTAT LM-OK Interrupt Register 3 (read-only) DTMF-KEY[4:0] Interrupt Register 4 (read-only CIS-BOF Checksum Register 1 (High Byte) (read-only) CHKSUM-H[6:0] ...
Page 169
... IM-DIS 19 BCR5 H UTDR-EN UTDX-EN 1A DSCR H DG-KEY[3:0] 1B reserved Data Sheet SLICOFI-2x Command Structure and Programming IO Control Register 1 IO Control Register 2 IO Control Register 3 Basic Configuration Register 1 SLEEP-EN REVPOL ACTR Basic Configuration Register 2 TTX-DIS TTX-12K HIM-AN Basic Configuration Register 3 PCM16K PCMX-EN CONFX-EN Basic Configuration Register 4 ...
Page 170
... PCMR3 H R3-HW 24 PCMR4 H R4-HW 25 PCMX1 H X1-HW Data Sheet SLICOFI-2x Command Structure and Programming Level Metering Configuration Register 1 LM-THM PCM2DC LM2 PCM Level Metering Configuration Register 2 LM-RECT RAMP-EN Level Metering Configuration Register 3 LM-ITIME[3:0] Offset Register 1 (High Byte) OFFSET-H[7:0] Offset Register 2 (Low Byte) ...
Page 171
... H PD-DC- TSTR3 TSTR4 H OPIM-AN OPIM-4M 2D TSTR5 Data Sheet SLICOFI-2x Command Structure and Programming PCM Transmit Register 2 X2-TS[6:0] PCM Transmit Register 3 X3-TS[6:0] PCM Transmit Register 4 X4-TS[6:0] Test Register 1 PD-AC-AD PD-AC-DA PD-AC-GN Test Register 2 PD-DC-AD PD-DC-DA PD-DCBUF Test Register 3 AC-DLB-4M AC-DLB- AC-DLB- 128K ...
Page 172
... Preliminary 6.2.1.2 SOP Register Description 00 REVISION Revision Number (read-only) H Bit 7 6 REV[7:0] Current revision number of the SLICOFI-2. 01 CHIPID 1 Chip Identification 1 (read-only) H Bit CHIPID 2 Chip Identification 2 (read-only) H Bit CHIPID 3 Chip Identification 3 (read-only) H Bit FUSE1 Fuse Register 1 H Bit 7 6 Data Sheet SLICOFI-2x Command Structure and Programming ...
Page 173
... Shifts the access edges by one clock cycle in double-clocking mode. SHIFT = 0 SHIFT = 1 PCMO[2:0] The whole PCM timing is moved by PCMO data periods against the FSC signal. PCMO[2: PCMO[2: PCMO[2: Data Sheet SLICOFI-2x Command Structure and Programming 5 4 SHIFT Figure 59 Single-clocking is used. Double-clocking is used. Figure 59 on ...
Page 174
... EDSP-EN Enables the Enhanced Digital Signal Processor EDSP. EDSP- EDSP- ASYNCH-R Enables asynchronous ringing in case of external ringing. ASYNCH ASYNCH Data Sheet SLICOFI-2x Command Structure and Programming Enhanced Digital Signal Processor is switched off. Enhanced Digital Signal Processor is switched on. External ringing with zero crossing selected. ...
Page 175
... Ground Key polarity. Indicating the active Ground Key level (positive/ negative) interrupt generation masked by the GNKP-M bit. A change of this bit generates an interrupt. This bit can be used to get information about interference voltage influence. GNKP = 0 GNKP = 1 Data Sheet SLICOFI-2x Command Structure and Programming GNDK GNKP ICON No interrupt in corresponding channel ...
Page 176
... Voltage at Ring/Tip is above the limit. Temperature at SLIC-E/-E2/-P is below the limit. Temperature at SLIC-E/-E2/-P is above the limit. In case of bit PDOT-DIS = 0 (register BCR2) the DuSLIC is switched automatically into PDH mode and OTEMP is hold at 1 until the SLICOFI-2 is set to PDH by a CIOP/CIDD command. Chapter Synchronization OK. Synchronization failure. ...
Page 177
... LM-OK bit changes from LM- LM- IO[4:1]-DU Data on IO pins filtered by DUP-IO counter and interrupt generation masked by the IO[4:1]-DU-M bits. A change of any of this bits generates an interrupt. Data Sheet SLICOFI-2x Command Structure and Programming LM-OK Chapter 3.7.2.1. Ramp generator active. Ramp generator not active. ...
Page 178
... A 770 1633 B Data Sheet SLICOFI-2x Command Structure and Programming DTMF-KEY[4:0] No valid DTMF Key was encountered by the DTMF receiver. A valid DTMF Key was encountered by the DTMF receiver. DTMF- DTMF- DTMF- KEY4 KEY3 KEY2 ...
Page 179
... C 941 1633 D UTDR-OK Universal Tone Detection Receive (e.g., Fax/Modem tones) UTDR- UTDR- UTDX-OK Universal Tone Detection Transmit (e.g., Fax/Modem tones) UTDX- UTDX- Data Sheet SLICOFI-2x Command Structure and Programming DTMF- DTMF- DTMF- KEY4 KEY3 KEY2 specific tone signal was detected. ...
Page 180
... Caller ID buffer overflow. An interrupt is only generated if the CIS-BOF bit changes from CIS-BOF = 0 CIS-BOF = 1 CIS-BUF Caller ID buffer underflow. An interrupt is only generated if the CIS-BUF bit changes from CIS-BUF = 0 CIS-BUF = 1 Data Sheet SLICOFI-2x Command Structure and Programming CIS- BOF operation. necessary to restart this DSP with bit EDSP-EN in the XCR register set ...
Page 181
... This is a status bit only. No interrupt will be generated. CIS-ACT = 0 CIS-ACT = 1 Data Sheet SLICOFI-2x Command Structure and Programming Caller ID data buffer requests no data. Caller ID data buffer requests more data to transmit, when the amount of data stored in the buffer is less than the buffer request size. ...
Page 182
... CRAM checksum high byte 0C CHKR2 Checksum Register 2 (Low Byte) H (read-only) Bit 7 6 CHKSUM-L[7:0] CRAM checksum low byte Data Sheet SLICOFI-2x Command Structure and Programming CHKSUM-H[6:0] For (cram_adr = 0 to 159) do cram_dat = cram[cram_adr] 1) csum[14:0] = (csum[13:0] & ‘0’) xor (‘0000000’ & cram_dat[7:0]) xor (‘ ...
Page 183
... LM-VAL-L[7:0] LM result low byte (selected by the LM-SEL bits in the LMCR2 register) 0F FUSE2 Fuse Register 2 H Bit FUSE3 Fuse Register 3 H Bit 7 6 Data Sheet SLICOFI-2x Command Structure and Programming LM-VAL-H[7: LM-VAL-L[7: for internal use only for internal use only 183 DuSLIC-E/-E2/-P ...
Page 184
... GNKP GNKP ICON-M Mask bit for Constant Current Information ICON bit ICON ICON_M = 1 VRTLIM-M Mask bit for Programmed Voltage Limit VRTLIM bit VRTLIM VRTLIM Data Sheet SLICOFI-2x Command Structure and Programming GNDK GNKP ICON - interrupt is generated if the READY bit changes from Changes of the READY bit don’ ...
Page 185
... OTEMP SYNC-M Mask bit for Synchronization Failure SYNC-FAIL bit SYNC SYNC Data Sheet SLICOFI-2x Command Structure and Programming A change of the OTEMP bit from generates an interrupt. A change of the OTEMP bit from doesn’t generate interrupts. A change of the SYNC-FAIL bit from generates an interrupt. ...
Page 186
... IO4 IO4 IO3-M Mask bit for IO3-DU bit IO3 IO3 Data Sheet SLICOFI-2x Command Structure and Programming Each change of the IO4 bit generates an interrupt. Changes of the IO4 bit don’t generate interrupts. Each change of the IO3 bit generates an interrupt. Changes of the IO3 bit don’t generate interrupts. ...
Page 187
... Mask bit for IO1-DU bit IO1 IO1 Data Sheet SLICOFI-2x Command Structure and Programming Each change of the IO2 bit generates an interrupt. Changes of the IO2 bit don’t generate interrupts. Each change of the IO1 bit generates an interrupt. Changes of the IO1 bit don’t generate interrupts. ...
Page 188
... Enabling output driver of the IO3 pin IO3-OEN = 0 IO3-OEN = 1 IO2-OEN Enabling output driver of the IO2 pin. If SLIC-P is selected (bits SEL-SLIC [1:0] in register BCR1 set to 01), pin IO2 cannot be controlled by the user but is utilized by the SLICOFI-2 to control the C3 input of SLIC-P. IO2-OEN = 0 IO2-OEN = 1 IO1-OEN Enabling output driver of the IO1 pin ...
Page 189
... ICON and VRTLIM in register INTREG1. The interval is programmable from 0 steps (reset value is 16.5 ms). Data Sheet SLICOFI-2x Command Structure and Programming The corresponding pin is driving a logic 0. The corresponding pin is driving a logic 1. The corresponding pin is driving a logic 0. The corresponding pin as driving a logic 1. ...
Page 190
... TIP wire is performed (HIT).If the HIR bit is set in addition to the HIT bit, the HIRT mode is activated. HIT = 0 HIT = 1 SLEEP-EN Enables Sleep mode of the DuSLIC channel. Valid only in the Power Down mode of the SLICOFI-2. SLEEP- SLEEP- REVPOL Reverses the polarity of DC feeding ...
Page 191
... SLIC-P SEL-SLIC[1: should be chosen. In this case internal unbalanced ringing in not needed and therefore there is no need to switch the C3 pin of the SLIC-P to 'High'. The C3 pin of the SLIC-P has be connected to GND and the IO2 pin of the SLICOFI-2 is free programmable for the user. ...
Page 192
... TTX-12K = 1 HIM-AN Higher impedance in analog impedance matching loop. HIM-AN corresponds to the coefficients calculated with DuSLICOS. If the coefficients are calculated with standard impedance in analog impedance matching loop, HIM-AN must be set the coefficients are calculated with high impedance in analog impedance matching loop, HIM-AN must be set to 1 ...
Page 193
... When over temperature is detected, the SLIC-E/-E2/ -P doesn’t automatically switch into Power Down High Impedance mode. In this case the output current of the SLIC-E/-E2/-P buffers is limited to a value which keeps the SLIC-E/-E2/-P temperature below the upper temperature limit. 193 ...
Page 194
... PCM16K = 0 PCM16K = 1 PCMX-EN Enables writing of subscriber voice data to the PCM highway. PCMX- PCMX- CONFX-EN Enables an external three-party conference. CONFX- External conference is disabled. CONFX- External conference is enabled. Data Sheet SLICOFI-2x Command Structure and Programming PCM16K PCMX- CONFX EN -EN A-Law enabled. -Law enabled. ...
Page 195
... Coefficients from CRAM are used for programmable filters and DC loop behavior. CRAM- CRAM- Data Sheet SLICOFI-2x Command Structure and Programming Chapter 5.1.1) are added and fed to analog output (see Three-party conferencing is not selected. Three-party conferencing is selected. Coefficients from ROM are used. ...
Page 196
... Disables the FRX filter. FRX-DIS = 0 FRX-DIS = 1 FRR-DIS Disables the FRR filter. FRR-DIS = 0 FRR-DIS = 1 HPX-DIS Disables the high-pass filter in transmit direction. HPX-DIS = 0 HPX-DIS = 1 Data Sheet SLICOFI-2x Command Structure and Programming AX-DIS AR-DIS FRX- DIS TH filter is enabled. TH filter is disabled ( filter is enabled. IM filter is disabled ( filter is enabled ...
Page 197
... Preliminary HPR-DIS Disables the high-pass filter in receive direction. HPR-DIS = 0 HPR-DIS = 1 Data Sheet SLICOFI-2x Command Structure and Programming High-pass filter is enabled. High-pass filter is disabled (H 197 DuSLIC-E/-E2/-P = 1). HPR 2000-07-14 ...
Page 198
... CIS-AUTO = 0 The Caller ID sender stops when CIS-EN is switched to 0. CIS-AUTO = 1 The Caller ID sender continues sending data until the CIS-EN Enables the Caller ID sender in the SLICOFI-2. Note: The Caller ID sender is configured directly by programming the according POP registers. Caller ID data are written byte RAM buffer ...
Page 199
... DTMF-SRC = 0 The Transmit path data (with or without LEC) is used for DTMF-SRC = 1 The Receive path data is used for the DTMF detection. DTMF-EN Enables the DTMF receiver of the SLICOFI-2. The DTMF receiver will be configured in a proper way by programming registers in the EDSP. DTMF- DTMF receiver is disabled. ...
Page 200
... COR8 Cuts off receive path at 8 kHz before the tone generator summation point. Allows sending of tone generator signals with no overlaid voice. COR8 = 0 COR8 = 1 Data Sheet SLICOFI-2x Command Structure and Programming 5 4 COR8 DG-KEY3 DG-KEY2 ...