PIC16F726-E/SO Microchip Technology, PIC16F726-E/SO Datasheet - Page 177

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PIC16F726-E/SO

Manufacturer Part Number
PIC16F726-E/SO
Description
14KB Flash Program, 1.8V-5.5V, 16MHz Internal Oscillator, 8b ADC, CCP, I2C/SPI,
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr

Specifications of PIC16F726-E/SO

Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
25
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 11 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPICE2000 - EMULATOR MPLAB-ICE 2000 POD
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
17.2
The SSP module, in I
functions, except general call support. It provides
interrupts on Start and Stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP module implements the I
specifications:
• I
• I
• Start and Stop bit interrupts enabled to support
• Address masking
Two pins are used for data transfer; the SCL pin (clock
line) and the SDA pin (data line). The user must
configure the two pin’s data direction bits as inputs in
the appropriate TRIS register. Upon enabling I
mode, the I
controlled by the SMP bit of SSPSTAT register. The
SSP module functions are enabled by setting the
SSPEN bit of SSPCON register.
Data is sampled on the rising edge and shifted out on
the falling edge of the clock. This ensures that the SDA
signal is valid during the SCL high time. The SCL clock
input must have minimum high and low times for proper
operation.
Specifications”.
FIGURE 17-7:
© 2009 Microchip Technology Inc.
firmware Master mode
2
2
C Slave mode (7-bit address)
C Slave mode (10-bit address)
SDA
SCL
I
2
C Mode
2
C slew rate limiters in the I/O pads are
Refer
Read
Shift
Clock
MSb
to
2
I
DIAGRAM
2
C mode, implements all slave
SSPMSK Reg
SSPADD Reg
Match Detect
C™ MODE BLOCK
Stop bit Detect
SSPBUF Reg
SSPSR Reg
Section 23.0
Start and
2
C Standard mode
LSb
Write
Addr Match
Internal
Data Bus
“Electrical
2
C
PIC16F72X/PIC16LF72X
FIGURE 17-8:
The SSP module has six registers for I
They are:
• SSP Control (SSPCON) register
• SSP Status (SSPSTAT) register
• Serial Receive/Transmit Buffer (SSPBUF) register
• SSP Shift Register (SSPSR), not directly
• SSP Address (SSPADD) register
• SSP Address Mask (SSPMSK) register
17.2.1
Selection of I
SSPCON register set, forces the SCL and SDA pins to
be open drain, provided these pins are programmed as
inputs by setting the appropriate TRISC bits. The SSP
module will override the input state with the output
data, when required, such as for Acknowledge and
slave-transmitter sequences.
accessible
Note:
Master
HARDWARE SETUP
Pull-up
externally to the SCL and SDA pins for
proper operation of the I
SDA
SCL
2
C mode, with the SSPEN bit of the
V
resistors
TYPICAL I
CONNECTIONS
DD
V
DD
must
2
DS41341E-page 177
C™
2
C module.
SDA
SDA
SCL
SCL
(optional)
Slave 1
Slave 2
be
2
C operation.
provided

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