S25FL032P0XMFI011 Spansion Inc., S25FL032P0XMFI011 Datasheet - Page 22

• Manufacturer Part Number: S25FL032P0XMFI011
• Description: IC 32M CMOS 3V 104MHZ SPI BUS INTERFACE
• Manufacturer: Spansion Inc.

Specifications of S25FL032P0XMFI011

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Bottom/Top
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC W
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 4M
• Supply Current: 38mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Compliant

9.
22
Command Definitions
The host system must shift all commands, addresses, and data in and out of the device, beginning with the
most significant bit. On the first rising edge of SCK after CS# is driven low, the device accepts the one-byte
command on SI (all commands are one byte long), most significant bit first. Each successive bit is latched on
the rising edge of SCK.
Every command sequence begins with a one-byte command code. The command may be followed by
address, data, both, or nothing, depending on the command. CS# must be driven high after the last bit of the
command sequence has been written.
The Read Data Bytes (READ), Read Data Bytes at Higher Speed (FAST_READ), Dual Output Read (DOR),
Quad Output Read (QOR), Dual I/O High Performance Read (DIOR), Quad I/O High Performance Read
(QIOR), Read Status Register (RDSR), Read Configuration Register (RCR), Read OTP Data (OTPR), Read
Manufacturer and Device ID (READ_ID), Read Identification (RDID) and Release from Deep Power-Down
and Read Electronic Signature (RES) command sequences are followed by a data output sequence on SO.
CS# can be driven high after any bit of the sequence is output to terminate the operation.
The Page Program (PP), Quad Page Program (QPP), 64 KB Sector Erase (SE), 4 KB Parameter Sector
Erase (P4E), 8 KB Parameter Sector Erase (P8E), Bulk Erase (BE), Write Status and Configuration Registers
(WRR), Program OTP space (OTPP), Write Enable (WREN), or Write Disable (WRDI) commands require that
CS# be driven high at a byte boundary, otherwise the command is not executed. Since a byte is composed of
eight bits, CS# must therefore be driven high when the number of clock pulses after CS# is driven low is an
exact multiple of eight.
The device ignores any attempt to access the memory array during a Write Registers, program, or erase
operation, and continues the operation uninterrupted.
The instruction set is listed in
Table 9.1
Table
lists the complete set of commands.
9.1.
S25FL032P
D a t a
S h e e t
S25FL032P_00_05 October 5, 2009