S25FL032P0XMFI011 Spansion Inc., S25FL032P0XMFI011 Datasheet - Page 53

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S25FL032P0XMFI011

Manufacturer Part Number
S25FL032P0XMFI011
Description
IC 32M CMOS 3V 104MHZ SPI BUS INTERFACE
Manufacturer
Spansion Inc.
Datasheet

Specifications of S25FL032P0XMFI011

Cell Type
NOR
Density
32Mb
Access Time (max)
8ns
Interface Type
Serial (SPI)
Boot Type
Bottom/Top
Address Bus
1b
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
-40C to 85C
Package Type
SOIC W
Sync/async
Synchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
4M
Supply Current
38mA
Mounting
Surface Mount
Pin Count
8
Lead Free Status / Rohs Status
Compliant

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11. Power-up and Power-down
October 5, 2009 S25FL032P_00_05
During power-up and power-down, certain conditions must be observed. CS# must follow the voltage applied
on V
(see
A pull-up resistor on Chip Select (CS#) typically meets proper power-up and power-down requirements.
No Read, Write Registers, program, or erase command should be sent to the device until V
V
the WEL bit is reset (0).
Each device in the host system should have the V
package pins (this capacitor is generally of the order of 0.1 µF), as a precaution to stabilizing the V
When V
operations are disabled and the device does not respond to any commands. Note that data corruption may
result if a power-down occurs while a Write Registers, program, or erase operation is in progress.
CC
At power-up, V
At power-down, GND
CC
min., plus a delay of t
Figure 11.1
, and must not be driven low to select the device until V
CC
drops from the operating voltage to below the minimum V
and
CC
V
V
(min.) plus a period of t
cc
cc
Table 11.1 on page
V
(max)
(min)
V
CC
V
V
CC
V
CC
CC
D a t a
(cut-off)
cc
PU
(max)
(low)
(min)
. At power-up, the device is in standby mode (not Deep Power-Down mode) and
Vcc
Figure 11.2 Power-down and Voltage Drop
Figure 11.1 Power-Up Timing Diagram
S h e e t
S25FL032P
54):
PU
t
CC
PU
No Device Access Allowed
rail decoupled by a suitable capacitor close to the
t
PD
CC
reaches the allowable values as follows
Full Device Access
CC
t
PU
threshold at power-down, all
Device Access
Allowed
Time
Time
CC
rises to the
CC
feed.
53

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