S25FL032P0XMFI011 Spansion Inc., S25FL032P0XMFI011 Datasheet - Page 27

• Manufacturer Part Number: S25FL032P0XMFI011
• Description: IC 32M CMOS 3V 104MHZ SPI BUS INTERFACE
• Manufacturer: Spansion Inc.

Specifications of S25FL032P0XMFI011

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Bottom/Top
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC W
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 4M
• Supply Current: 38mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Compliant

9.4
October 5, 2009 S25FL032P_00_05
Quad Output Read Mode (QOR)
The Quad Output Read instruction is similar to the FAST_READ instruction, except that the data is shifted out
4 bits at a time using 4 pins (SI/IO0, SO/IO1, W#/ACC/IO2 and HOLD#/IO3) instead of 1 bit, at a maximum
frequency of 80 MHz. The Quad Output Read mode effectively doubles the data transfer rate compared to the
Dual Output Read instruction, and is four times the data transfer rate of the FAST_READ instruction.
The host system must first select the device by driving CS# low. The Quad Output Read command is then
written to SI, followed by a 3-byte address (A23-A0) and a dummy byte. Each bit is latched on the rising edge
of SCK. Then the memory contents, at the address that are given, are shifted out four bits at a time through
IO0 (SI), IO1 (SO), IO2 (W#/ACC), and IO3 (HOLD#) pins at a frequency f
The Quad Output Read command sequence is shown in
address byte specified can start at any location of the memory array. The device automatically increments to
the next higher address after each byte of data is output. The entire memory array can therefore be read with
a single Quad Output Read command. When the highest address is reached, the address counter reverts to
00000h, allowing the read sequence to continue indefinitely.
It is important that the I/O pins be set to high-impedance prior to the falling edge of the first data out clock.
The Quad Output Read command is terminated by driving CS# high at any time during data output. The
device rejects any Quad Output Read command issued while it is executing a program, erase, or Write
Registers operation, and continues the operation uninterrupted.
The Quad bit of Configuration Register must be set (CR Bit1 = 1) to enable the Quad mode capability of the
S25FL device.
W#/ACC/IO2
HOLD#/IO3
SO/IO1
SI/IO0
SCK
CS#
0 1 2 3 4 5 6 7 8 9 10
Instruction
D a t a
Hi-Z
Hi-Z
Hi-Z
Figure 9.4 Quad Output Read Instruction Sequence
S h e e t
23
*
S25FL032P
22 21
Address
24 Bit
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
3 2 1 0 7 6 5 4 3 2
Figure 9.4
Dummy Byte
and
*
1 0
Table 9.1 on page
C
on the falling edge of SCK.
OUT 1
4
5
6
7
*
DATA
0
3
1
2
SI Switches from Input to Output
OUT 2
5
DATA
4 0
6
7
*
1
2
3 7
OUT 3
5
*
4 0
6
DATA
1
2
3
23. The first
OUT 4
5
6
DATA
4 0
7
*
2
1
3 7
4
*
6
5
*MSB
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