S25FL032P0XMFI011 Spansion Inc., S25FL032P0XMFI011 Datasheet - Page 36

• Manufacturer Part Number: S25FL032P0XMFI011
• Description: IC 32M CMOS 3V 104MHZ SPI BUS INTERFACE
• Manufacturer: Spansion Inc.

Specifications of S25FL032P0XMFI011

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Bottom/Top
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC W
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 4M
• Supply Current: 38mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Compliant

9.9
9.10
36
Write Enable (WREN)
Write Disable (WRDI)
The Write Enable (WREN) command (see
enables the device to accept a Write Status Register, program, or erase command. The WEL bit must be set
prior to every Page Program (PP), Quad Page Program (QPP), Parameter Sector Erase (P4E, P8E), Erase
(SE or BE), Write Registers (WRR) and OTP Program (OTPP) command.
The host system must first drive CS# low, write the WREN command, and then drive CS# high.
The Write Disable (WRDI) command (see
disables the device from accepting a Page Program (PP), Quad Page Program (QPP), Parameter Sector
Erase (P4E, P8E), Erase (SE, BE), Write Registers (WRR) and OTP Program (OTPP) command. The host
system must first drive CS# low, write the WRDI command, and then drive CS# high.
Any of following conditions resets the WEL bit:
Power-up
Write Disable (WRDI) command completion
Write Registers (WRR) command completion
Page Program (PP) command completion
Quad Page Program (QPP) completion
Parameter Sector Erase (P4E, P8E) completion
Sector Erase (SE) command completion
Bulk Erase (BE) command completion
OTP Program (OTPP) completion
CS#
SCK
SO
SI
Figure 9.11 Write Enable (WREN) Command Sequence
Figure 9.12 Write Disable (WRDI) Command Sequence
SCK
CS#
SO
SI
Mode 3
Mode 0
Mode 3
Mode 0
Hi-Z
Hi-Z
S25FL032P
Figure
Figure
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
D a t a
9.12) resets the Write Enable Latch (WEL) bit to a 0, which
9.11) sets the Write Enable Latch (WEL) bit to a 1, which
Command
Command
S h e e t
S25FL032P_00_05 October 5, 2009