S25FL032P0XMFI011 Spansion Inc., S25FL032P0XMFI011 Datasheet - Page 48

• Manufacturer Part Number: S25FL032P0XMFI011
• Description: IC 32M CMOS 3V 104MHZ SPI BUS INTERFACE
• Manufacturer: Spansion Inc.

Specifications of S25FL032P0XMFI011

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Bottom/Top
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC W
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 4M
• Supply Current: 38mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Compliant

9.21
48
9.20.1
Clear Status Register (CLSR)
Release from Deep Power-Down and Read Electronic Signature (RES)
The device features an 8-bit Electronic Signature, which can be read using the RES command. See
Figure 9.24
Signature is not to be confused with the identification data obtained using the RDID command. The device
offers the Electronic Signature so that it can be used with previous devices that offered it; however, the
Electronic Signature should not be used for new designs, which should read the RDID data instead.
After the host system drives CS# low, it must write the RES command followed by 3 dummy bytes to SI (each
bit is latched on SI during the rising edge of SCK). The Electronic Signature is then output on SO; each bit is
shifted out on the falling edge of SCK. The RES operation is terminated by driving CS# high after the
Electronic Signature is read at least once. Additional clock cycles on SCK with CS# low cause the device to
output the Electronic Signature repeatedly.
When CS# is driven high, the device transitions from DP mode to the standby mode after a delay of t
previously described. The RES command always provides access to the Electronic Signature of the device
and can be applied even if DP mode has not been entered.
Any RES command issued while an erase, program, or Write Registers operation is in progress not executed,
and the operation continues uninterrupted.
The Clear Status Register command resets bit SR5 (Erase Fail Flag) and bit SR6 (Program Fail Flag). It is not
necessary to set the WEL bit before the Clear SR Fail Flags command is executed. The WEL bit will be
unchanged after this command is executed. This command also resets the State machine and loads latches
SCK
CS#
SO
SI
Hi-Z
and
Figure 9.24 Release from Deep Power-Down and RES Command Sequence
Table 9.1 on page 23
SCK
CS S #
SI
0
Figure 9.25 Clear Status Register (CLSR) Instruction Sequence
1
2
Command
3
4
5
6
for the command sequence and signature value. The Electronic
S25FL032P
7
0
MSB
23 22 21
8
D a t a
9 10
1
3 Dummy Bytes
2
28 29 30 31 32 33 34 35 36 37 38
3 2
Deep Power-Down Mode
Instruction
S h e e t
3
1
4
0
MSB
7
5
6
6
5
Electronic ID
4
S25FL032P_00_05 October 5, 2009
7
3
2
1
39
0
t
RES
Standby Mode
RES
, as