AM79C973BKD AMD (ADVANCED MICRO DEVICES), AM79C973BKD Datasheet - Page 163

• Manufacturer Part Number: AM79C973BKD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD

• Lead Free Status / RoHS Status: Compliant

8
7
APROMWE Address PROM Write Enable.
INTLEVEL
value in the D5 bit position (see
Appendix B on SMIU Bus Fre-
quency.
Read/Write accessible always.
I2C_M2 is cleared by H_RESET
and is unaffected by S_RESET or
by setting the STOP bit.
The Am79C973/Am79C975 con-
troller contains a shadow RAM on
board for storage of the first 16
bytes loaded from the serial EE-
PROM.
PROM I/O Resources will be di-
rected toward this RAM. When
APROMWE is set to 1, then write
access to the shadow RAM will
be enabled.
Interrupt Level. This bit allows the
interrupt output signals to be pro-
grammed for level or edge-
sensitive applications.
Read/Write accessible always.
APROMWE is cleared to 0 by
H_RESET and is unaffected by
S_RESET or by setting the STOP
bit.
When INTLEVEL is cleared to 0,
the INTA pin is configured for
level-sensitive applications. In
this mode, an interrupt request is
signaled by a low level driven on
the INTA pin by the Am79C973/
Am79C975 controller. When the
interrupt is cleared, the INTA pin
is tri-stated by the Am79C973/
Am79C975 controller and al-
lowed to be pulled to a high level
by an external pullup device. This
mode is intended for systems
which allow the interrupt signal to
be shared by multiple devices.
When INTLEVEL is set to 1, the
INTA pin is configured for edge-
sensitive applications. In this
mode, an interrupt request is sig-
naled by a high level driven on
the INTA pin by the Am79C973/
Am79C975 controller. When the
interrupt is cleared, the INTA pin
is driven to a low level by the
Am79C973/Am79C975 control-
ler. This mode is intended for sys-
Accesses to Address
P R E L I M I N A R Y
Am79C973/Am79C975
6
5
4
3
I2C_M1
I2C_M0
I2C_N2
EADISEL
(Am79C975 only). This bit is used
(Am79C975 only). This bit is used
(Am79C975 only). This bit is used
tems that do not allow
channels to be shared by multiple
devices.
INTLEVEL should not be set to 1
when the Am79C973/Am79C975
controller is used in a PCI bus ap-
plication.
Read/Write accessible always.
INTLEVEL is cleared to 0 by
H_RESET and is unaffected by
S_RESET or by setting the STOP
bit.
to set the operating frequency of
the SMIU core. It represents the
value in the D4 bit position (see
Appendix B on SMIU Bus Fre-
quency.
Read/Write accessible always.
I2C_M1 is cleared by H_RESET
and is unaffected by S_RESET or
by setting the STOP bit.
to set the operating frequency of
the SMIU core. It represents the
value in the D3 bit position (see
Appendix B on SMIU Bus Fre-
quency.
Read/Write accessible always.
I2C_M0 is cleared by H_RESET
and is unaffected by S_RESET or
by setting the STOP bit.
to set the operating frequency of
the SMIU core. It represents the
value in the D2 bit position (see
Appendix B on SMIU Bus Fre-
quency.
Read/Write accessible always.
I2C_N2 is cleared by H_RESET
and is unaffected by S_RESET or
by setting the STOP bit.
EADI Select. When set to 1, this
bit enables the three EADI inter-
face pins that are multiplexed
with other functions. EESK/LED1
becomes SFBD, EEDO/LED3
becomes
LED2 becomes MIIRXFRTGE.
MIIRXFRTGD,
interrupt
163
and