AM79C973BKD AMD (ADVANCED MICRO DEVICES), AM79C973BKD Datasheet - Page 175

• Manufacturer Part Number: AM79C973BKD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD

• Lead Free Status / RoHS Status: Compliant

4-3
2-0
PHYSEL [1:0]
PHYSEL[1:0]
LINBC
00
01
10
11
Expansion ROM/Flash - Normal Mode
EADI/Internal MII Snoop Mode
Full MII Mode - An External PHY
Required
Reserved
PHYSEL[1:0] bits allow for soft-
ware controlled selection of differ-
ent operation and test modes.
The normal mode of operation is
when both bits 0 and 1 are set to
0 to select the Expansion ROM/
Flash. Setting bit 0 to 1 and bit 1
to 0 allows snooping of the inter-
nal MII-compatible bus to allow
External Address Detection Inter-
face
SEL[1:0]
external MII mode. Since the in-
ternal 10/100 PHY is disabled in
this
Am79C975 controller behaves
like an Am79C972 PCnet-FAST+
device. Tehese controllers are
not designed to support two
PHYs at a time as only one PHY
can be used at a given time. An
external or internal PHY can be
used by reconfiguring the EE-
PROM or the BCI18 register. See
the following table for details.
Read accessible always, these
bits can only be written from the
EEPROM unless a write-enable
bit BCR2[13], is set. PHYSEL
[1:0] is cleared by H_RESET and
is not affected by S_RESET or
STOP.
Reserved locations. Read acces-
sible always; write accessible
only when either the STOP or the
SPND bit is set. After H_RESET,
the value in these bits will be
001b. The setting of these bits
have
Am79C973/Am79C975 controller
function. LINBC is not affected by
S_RESET or STOP.
and is not affected by S_RESET
or STOP.
mode,
(EADI).
no
=
Mode
effect
10
the
Setting
enables
Am79C973/
P R E L I M I N A R Y
on
Am79C973/Am79C975
PHY-
any
the
BCR19: EEPROM Control and Status
Bit
31-16 RES
15
PVALID
Name
Reserved locations. Written as
zeros and read as undefined.
EEPROM Valid status bit. Read
accessible only. PVALID is read
only; write operations have no ef-
fect. A value of 1 in this bit indi-
cates that a PREAD operation
has occurred, and that (1) there is
an EEPROM connected to the
Am79C973/Am79C975 controller
interface pins and (2) the con-
tents read from the EEPROM
have passed the checksum verifi-
cation operation.
A value of 0 in this bit indicates a
failure in reading the EEPROM.
The checksum for the entire 82
bytes of EEPROM is incorrect or
no EEPROM is connected to the
interface pins.
PVALID is set to 0 during
H_RESET and is unaffected by
S_RESET or the STOP bit. How-
ever, following the H_RESET op-
eration, an automatic read of the
EEPROM will be performed. Just
as is true for the normal PREAD
command, at the end of this auto-
matic read operation, the PVALID
bit may be set to 1. Therefore,
H_RESET will set the PVALID bit
to 0 at first, but the automatic EE-
PROM read operation may later
set PVALID to a 1.
If PVALID becomes 0 following
an EEPROM read operation (ei-
ther automatically generated af-
ter
through PREAD), then all EE-
PROM-programmable BCR loca-
tions will be reset to their
H_RESET values. The content of
the Address PROM locations,
however, will not be cleared.
If no EEPROM is present at the
EESK, EEDI, and EEDO pins,
then all attempted PREAD com-
mands will terminate early and
PVALID will not be set. This ap-
plies to the automatic read of the
Description
H_RESET,
or
requested
175