AM79C973BKD AMD (ADVANCED MICRO DEVICES), AM79C973BKD Datasheet - Page 75

• Manufacturer Part Number: AM79C973BKD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD

• Lead Free Status / RoHS Status: Compliant

start of transmission (including preamble) will be auto-
matically retried with no host intervention. The transmit
FIFO ensures this by guaranteeing that data contained
within the FIFO will not be overwritten until at least 64
bytes (512 bits) of preamble plus address, length, and
data fields have been transmitted onto the network
without encountering a collision. Note that if DRTY
(CSR15, bit 5) is set to 1 or if the network interface is
operating in full-duplex mode, no collision handling is
required, and any byte of frame data in the FIFO can be
overwritten as soon as it is transmitted.
If 16 total attempts (initial attempt plus 15 retries) fail,
the Am79C973/Am79C975 controller sets the RTRY bit
in the current transmit TDTE in host memory (TMD2),
gives up ownership (resets the OWN bit to 0) for this
frame, and processes the next frame in the transmit
ring for transmission.
Abnormal network conditions include:
These conditions should not occur on a correctly con-
figured IEEE 802.3 network operating in half-duplex
mode. If they do, they will be reported. None of these
conditions will occur on a network operating in full-
duplex mode. (See the section Full-Duplex Operation
for more detail.)
When an error occurs in the middle of a multi-buffer
frame transmission, the error status will be written in the
current descriptor. The OWN bit(s) in the subsequent
descriptor(s) will be cleared until the STP (the next
frame) is found.
Loss of Carrier
LCAR will be reported for every frame transmitted if the
controller detects a loss of carrier.
Late Collision
A late collision will be reported if a collision condition
occurs after one slot time (512 bit times) after the trans-
mit process was initiated (first bit of preamble com-
menced). The Am79C973/Am79C975 controller will
abandon the transmit process for that frame, set Late
Collision (LCOL) in the associated TMD2, and process
the next transmit frame in the ring. Frames experienc-
ing a late collision will not be retried. Recovery from this
condition must be performed by upper layer software.
SQE Test Error
CERR will be asserted in the 10BASE-T mode after
transmit, if the network port is in Link Fail state. CERR
will never cause INTA to be activated. It will, however,
set the ERR bit CSR0.
Loss of carrier
Late collision
SQE Test Error (Does not apply to 100-Mbps net-
works.)
P R E L I M I N A R Y
Am79C973/Am79C975
Receive Operation
The receive operation and features of the Am79C973/
Am79C975 controller are controlled by programmable
options. The Am79C973/Am79C975 controller offers a
large receive FIFO to provide frame buffering for in-
creased system latency, automatic flushing of collision
fragments (runt packets), automatic receive pad strip-
ping, and a variety of address match options.
Receive Function Programming
Automatic pad field stripping is enabled by setting the
ASTRP_RCV bit in CSR4. This can provide flexibility in
the reception of messages using the IEEE 802.3 frame
format.
All receive frames can be accepted by setting the
PROM bit in CSR15. Acceptance of unicast and broad-
cast frames can be individually turned off by setting the
DRCVPA or DRCVBC bits in CSR15. The Physical Ad-
dress register (CSR12 to CSR14) stores the address
that the Am79C973/Am79C975 controller compares to
the destination address of the incoming frame for a uni-
cast address match. The Logical Address Filter register
(CSR8 to CSR11) serves as a hash filter for multicast
address match.
The point at which the BMU will start to transfer data
from the receive FIFO to buffer memory is controlled by
the RCVFW bits in CSR80. The default established
during H_RESET is 01b, which sets the watermark flag
at 64 bytes filled.
For test purposes, the Am79C973/Am79C975 control-
ler can be programmed to accept runt packets by set-
ting RPA in CSR124.
Address Matching
The Am79C973/Am79C975 controller supports three
types of address matching: unicast, multicast, and
broadcast. The normal address matching procedure
can be modified by programming three bits in CSR15,
the mode register (PROM, DRCVPA, and DRCVBC).
If the first bit received after the SFD (the least signifi-
cant bit of the first byte of the destination address field)
is 0, the frame is unicast, which indicates that the frame
is meant to be received by a single node. If the first bit
received is 1, the frame is multicast, which indicates
that the frame is meant to be received by a group of
nodes. If the destination address field contains all 1s,
the frame is broadcast, which is a special type of multi-
cast. Frames with the broadcast address in the destina-
tion address field are meant to be received by all nodes
on the local area network.
When a unicast frame arrives at the Am79C973/
Am79C975 controller, the controller will accept the
frame if the destination address field of the incoming
frame exactly matches the 6-byte station address
stored in the Physical Address registers (PADR,
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