AM79C973BKD AMD (ADVANCED MICRO DEVICES), AM79C973BKD Datasheet - Page 207

• Manufacturer Part Number: AM79C973BKD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD

• Lead Free Status / RoHS Status: Compliant

25
24
23
STP
ENP
BPE
while data chaining a received
frame. This can occur in either of
two ways:
Start of Packet indicates that this
is the first buffer used by the
Am79C973/Am79C975 controller
for this frame. If STP and ENP
are both set to 1, the frame fits
into a single buffer. Otherwise,
the frame is spread over more
than one buffer. When LAPPEN
(CSR3, bit 5) is cleared to 0, STP
is
Am79C975
cleared by the host. When LAP-
PEN is set to 1, STP must be set
by the host.
End of Packet indicates that this
is the last buffer used by the
Am79C973/Am79C975 controller
for this frame. It is used for data
chaining buffers. If both STP and
ENP are set, the frame fits into
one buffer and there is no data
chaining. ENP is set by the
Am79C973/Am79C975 controller
and cleared by the host.
Bus Parity Error is set by the
Am79C973/Am79C975 controller
when a parity error occurred on
the bus interface during data
transfers to a receive buffer. BPE
is valid only when ENP, OFLO, or
BUFF are set. The Am79C973/
Am79C975 controller will only set
BPE when the advanced parity
error handling is enabled by set-
1. The OWN bit of the next buffer
2. FIFO overflow occurred before
If a Buffer Error occurs, an Over-
flow Error may also occur inter-
nally in the FIFO, but will not be
reported in the descriptor status
entry unless both BUFF and
OFLO errors occur at the same
time.
Am79C973/Am79C975 controller
and cleared by the host.
is 0.
the
controller was able to read the
OWN bit of the next descrip-
tor.
set
BUFF
Am79C973/Am79C975
by
the
is
controller
set
Am79C973/
P R E L I M I N A R Y
Am79C973/Am79C975
by
and
the
22
21
PAM
LAFM
ting APERREN (BCR20, bit 10) to
1. BPE is set by the Am79C973/
Am79C975
cleared by the host.
This bit does not exist when the
Am79C973/Am79C975 controller
is programmed to use 16-bit soft-
ware structures for the descriptor
ring entries (BCR20, bits 7-0,
SWSTYLE is cleared to 0).
Physical Address Match is set by
the Am79C973/Am79C975 con-
troller when it accepts the re-
ceived frame due to a match of
the frame’s destination address
with the content of the physical
address register. PAM is valid
only when ENP is set. PAM is set
by the Am79C973/Am79C975
controller and cleared by the
host.
This bit does not exist when the
Am79C973/Am79C975 controller
is programmed to use 16-bit soft-
ware structures for the descriptor
ring entries (BCR20, bits 7-0,
SWSTYLE is cleared to 0).
Logical Address Filter Match is
set
Am79C975 controller when it ac-
cepts the received frame based
on the value in the logical ad-
dress filter register. LAFM is valid
only when ENP is set. LAFM is
set
Am79C975
cleared by the host.
Note that if DRCVBC (CSR15, bit
14) is cleared to 0, only BAM, but
not LAFM will be set when a
Broadcast frame is received,
even if the Logical Address Filter
is programmed in such a way that
a Broadcast frame would pass
the hash filter. If DRCVBC is set
to 1 and the Logical Address Fil-
ter is programmed in such a way
that a Broadcast frame would
pass the hash filter, LAFM will be
set on the reception of a Broad-
cast frame.
This bit does not exist when the
Am79C973/Am79C975 controller
by
by
the
the
controller
controller
Am79C973/
Am79C973/
207
and
and