MT45W4MW16PCGA-70 IT Micron Technology Inc, MT45W4MW16PCGA-70 IT Datasheet - Page 11

• Manufacturer Part Number: MT45W4MW16PCGA-70 IT
• Manufacturer: Micron Technology Inc

Specifications of MT45W4MW16PCGA-70 IT

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Sleep Mode (CR[4]) Default = PAR Enabled
Page Mode Operation (CR[7]) Default = Disabled
Device Identification Register (DIDR)
Table 4:
Access Using ZZ#
Figure 10:
PDF: 09005aef81f0698d / Source: 09005aef81f06935
64mb_asyncpage_cr1_0_p25z.fm - Rev. D 7/09 EN
Bit Field
Field name
Bit setting
Meaning
Device Identification Register Mapping
Load Configuration Register Operation
Row length
128 words
DIDR[15]
Notes:
0b
The sleep mode bit determines which low-power mode is to be entered when ZZ# is
driven LOW. If CR[4] = 1, PAR operation is enabled. If CR[4] = 0, DPD operation is
enabled. PAR can also be enabled directly by writing to the CR using the software access
sequence. Note that this then disables ZZ# initiation of PAR. DPD cannot be enabled or
disabled using the software access sequence; the DPD setting can be changed only by
using ZZ# to access the CR.
The page mode operation bit determines whether page mode is enabled for READ oper-
ations. In the power-up default state, page mode is disabled.
The DIDR provides information on the device manufacturer, CellularRAM generation,
and the specific device configuration. The DIDR is not part of the CellularRAM 1.0 Work-
group specification. Table 4 describes the bit fields in the DIDR.
The DIDR is accessed through the register access software sequence with DQ = 0002h on
the third cycle.
1. CellularRAM generation is shown as 010b and has no meaning in terms of this device.
The CR can be loaded using a WRITE operation immediately after ZZ# makes a HIGH-
to-LOW transition (Figure 10). The values placed on addresses A[21:0] are latched into
the CR on the rising edge of CE# or WE#, whichever occurs first. LB#/UB# are “Don’t
Care.” Access using ZZ# is WRITE only.
Address
WE#
CE#
ZZ#
0000b
0001b
…
Device version
DIDR[14:11]
t < 500ns
2nd
1st
…
Address Valid
64Mb: 4 Meg x 16 Async/Page CellularRAM 1.0
Device density
11
DIDR[10:8]
64Mb
010b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CellularRAM generation
DIDR[7:5]
010b
n/a
1
©2005 Micron Technology, Inc. All rights reserved.
Device Registers
DIDR[4:0]
Vendor ID
00011b
Micron