NH82801ERSL8WB Intel, NH82801ERSL8WB Datasheet - Page 103
NH82801ERSL8WB
Manufacturer Part Number
NH82801ERSL8WB
Description
Manufacturer
Intel
Datasheet
1.NH82801ERSL8WB.pdf
(671 pages)
Specifications of NH82801ERSL8WB
Lead Free Status / RoHS Status
Compliant
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5.4
5.4.1
Intel
®
Figure 10. LPC Interface Diagram
82801EB ICH5 / 82801ER ICH5R Datasheet
LPC Bridge (w/ System and Management Functions)
(D31:F0)
The LPC Bridge function of the ICH5 resides in PCI Device 31:Function 0. In addition to the LPC
bridge function, D31:F0 contains other functional units including DMA, Interrupt controllers,
Timers, Power Management, System Management, GPIO, and RTC. In this chapter, registers and
functions associated with other functional units (power management, GPIO, USB, IDE, etc.) are
described in their respective sections.
LPC Interface
The ICH5 implements an LPC interface as described in the Low Pin Count Interface Specification,
Revision 1.1. The LPC interface to the ICH5 is shown in
all of the signals that are shown as optional, but peripherals are not required to do so.
ICH
SUS_STAT#
GPI
LFRAME#
PCI Bus
LPCPD#
LAD[3:0]
LDRQ#
(optional)
(optional)
(optional)
LSMI#
PCI
CLK
PCI
RST#
Figure
Super I/O
10. Note that the ICH5 implements
Functional Description
PCI
SERIRQ
PCI
PME#
103
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