NH82801ERSL8WB Intel, NH82801ERSL8WB Datasheet - Page 192
NH82801ERSL8WB
Manufacturer Part Number
NH82801ERSL8WB
Description
Manufacturer
Intel
Datasheet
1.NH82801ERSL8WB.pdf
(671 pages)
Specifications of NH82801ERSL8WB
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Functional Description
5.19
5.19.1
5.19.1.1
192
Table 81. Frame List Pointer Bit Description
USB UHCI Host Controllers (D29:F0, F1, F2, and F3)
The ICH5 contains four USB 2.0 full/low speed host controllers that support the standard Universal
Host Controller Interface (UHCI), Revision 1.1. Each UHCI Host Controller (UHC) includes a root
hub with two separate USB ports each, for a total of 8 USB ports.
Data Structures in Main Memory
This section describes the details of the data structures used to communicate control, status, and
data between software and the ICH5: Frame Lists, Transfer Descriptors, and Queue Heads. Frame
Lists are aligned on 4-KB boundaries. Transfer Descriptors and Queue Heads are aligned on
16-byte boundaries.
Frame List Pointer
The frame list pointer contains a link pointer to the first data object to be processed in the frame, as
well as the control bits defined in
•
•
•
31:4
Bit
3:2
1
0
Overcurrent detection on all eight USB ports is supported. The overcurrent inputs are 5 V
tolerant, and can be used as GPIs if not needed.
The ICH5’s UHCI host controllers are arbitrated differently than standard PCI devices to
improve arbitration latency.
The UHCI controllers use the Analog Front End (AFE) embedded cell that allows support for
USB high speed signaling rates, instead of USB I/O buffers.
Frame List Pointer (FLP). This field contains the address of the first data object to be processed in
the frame and corresponds to memory address signals [31:4], respectively.
Reserved. These bits must be written as 0.
QH/TD Select (Q). This bit indicates to the hardware whether the item referenced by the link pointer
is a TD (Transfer Descriptor) or a QH (Queue Head). This allows the Intel
proper type of processing on the item after it is fetched.
0 = TD
1 = QH
Terminate (T). This bit indicates to the ICH5 whether the schedule for this frame has valid entries in
it.
0 = Pointer is valid (points to a QH or TD).
1 = Empty Frame (pointer is invalid).
Table
81.
Description
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
®
ICH5 to perform the
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