NH82801ERSL8WB Intel, NH82801ERSL8WB Datasheet - Page 359
NH82801ERSL8WB
Manufacturer Part Number
NH82801ERSL8WB
Description
Manufacturer
Intel
Datasheet
1.NH82801ERSL8WB.pdf
(671 pages)
Specifications of NH82801ERSL8WB
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9.4.7
9.4.8
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
OCW1—Operational Control Word 1 (Interrupt Mask)
Register (LPC I/F—D31:F0)
Offset Address:
Default Value:
OCW2—Operational Control Word 2 Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Following a part reset or ICW initialization, the controller enters the fully nested mode of
operation. Non-specific EOI without rotation is the default. Both rotation mode and specific EOI
mode are disabled following initialization.
Bit
7:0
Bit
7:5
4:3
2:0
Interrupt Request Mask — R/W. When a 1 is written to any bit in this register, the corresponding
IRQ line is masked. When a 0 is written to any bit in this register, the corresponding IRQ mask bit is
cleared, and interrupt requests will again be accepted by the controller. Masking IRQ2 on the master
controller will also mask the interrupt requests from the slave controller.
Rotate and EOI Codes (R, SL, EOI) — WO. These three bits control the Rotate and End of Interrupt
modes and combinations of the two.
000 = Rotate in Auto EOI Mode (Clear)
001 = Non-specific EOI command
010 = No Operation
011 =
100 = Rotate in Auto EOI Mode (Set)
101 = Rotate on Non-Specific EOI Command
110 =
111 =
†
OCW2 Select — WO. When selecting OCW2, bits 4:3 = 00
Interrupt Level Select (L2, L1, L0) — WO. L2, L1, and L0 determine the interrupt level acted upon
when the SL bit is active. A simple binary code, outlined below, selects the channel for the command
to act upon. When the SL bit is inactive, these bits do not have a defined function; programming L2,
L1 and L0 to 0 is sufficient in this case.
Bits
000
001
010
011
L0 – L2 Are Used
†
†
†
Interrupt Level
IRQ0/8
IRQ1/9
IRQ2/10
IRQ3/11
Rotate on Specific EOI Command
Specific EOI Command
Set Priority Command
Master Controller
Slave Controller
00h
Master Controller
Slave Controller
Bit[4:0]=undefined, Bit[7:5]=001
Bits
100
101
110
111
–
–
–
–
0A1h
0A0h
021h
020h
Interrupt Level
IRQ4/12
IRQ5/13
IRQ6/14
IRQ7/15
Description
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Attribute:
Size:
R/W
8 bits
WO
8 bits
359
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