NH82801ERSL8WB Intel, NH82801ERSL8WB Datasheet - Page 438
NH82801ERSL8WB
Manufacturer Part Number
NH82801ERSL8WB
Description
Manufacturer
Intel
Datasheet
1.NH82801ERSL8WB.pdf
(671 pages)
Specifications of NH82801ERSL8WB
Lead Free Status / RoHS Status
Compliant
- Current page: 438 of 671
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SATA Controller Registers (D31:F2)
11.1.8
11.1.9
11.1.10
.
438
BCC—Base Class Code Register
(SATA–D31:F2)
Address Offset:
Default Value:
PMLT—Primary Master Latency Timer Register
(SATA–D31:F2)
Address Offset:
Default Value:
PCMD_BAR—Primary Command Block Base Address
Register (SATA–D31:F2)
Address Offset:
Default Value:
NOTE: This 8-byte I/O space is used in native mode for the Primary Controller’s Command Block.
31:16
15:3
Bit
2:1
Bit
7:0
Bit
7:0
0
Reserved
Base Address — R/W. This field provides the base address of the I/O space (eight, consecutive I/O
locations).
Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O space.
Base Class Code (BCC) — RO.
01h = Mass storage device
Master Latency Timer Count (MLTC) — RO.
00h = Hardwired. The IDE controller is implemented internally, and is not arbitrated as a PCI device,
so it does not need a Master Latency Timer.
0Bh
01h
0Dh
00h
10h
00000001h
–
13h
Description
Intel
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
RO
8 bits
RO
8 bits
R/W, RO
32 bits
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