NH82801ERSL8WB Intel, NH82801ERSL8WB Datasheet - Page 565
NH82801ERSL8WB
Manufacturer Part Number
NH82801ERSL8WB
Description
Manufacturer
Intel
Datasheet
1.NH82801ERSL8WB.pdf
(671 pages)
Specifications of NH82801ERSL8WB
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Compliant
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16.1.12
16.1.13
16.1.14
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
SVID—Subsystem Vendor Identification Register
(Modem—D31:F6)
Address Offset:
Default Value:
Lockable:
The SVID register, in combination with the Subsystem ID register, enable the operating
environment to distinguish one audio subsystem from the other(s). This register is implemented as
write-once register. Once a value is written to it, the value can be read back. Any subsequent writes
will have no effect.
This register is not affected by the D3
SID—Subsystem Identification Register
(Modem—D31:F6)
Address Offset:
Default Value:
Lockable:
The SID register, in combination with the Subsystem Vendor ID register make it possible for the
operating environment to distinguish one audio subsystem from another. This register is
implemented as write-once register. Once a value is written to it, the value can be read back. Any
subsequent writes will have no effect.
This register is not affected by the D3
CAP_PTR—Capabilities Pointer Register
(Modem—D31:F6)
Address Offset:
Default Value:
Lockable:
This register indicates the offset for the capability pointer.
15:0
15:0
Bit
7:0
Bit
Bit
Capabilities Pointer (CAP_PTR) — RO. This field indicates that the first capability pointer offset is
offset 50h.
Subsystem Vendor ID — R/WO.
Subsystem ID — R/WO.
2C
0000h
No
2E
0000h
No
34h
50h
No
–
–
2Fh
2Dh
HOT
HOT
to D0 transition.
to D0 transition.
AC ’97 Modem Controller Registers (D31:F6)
Description
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
R/WO
16 bits
Core
R/WO
16 bits
Core
RO
8 bits
Core
565
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