NH82801ERSL8WB Intel, NH82801ERSL8WB Datasheet - Page 521
NH82801ERSL8WB
Manufacturer Part Number
NH82801ERSL8WB
Description
Manufacturer
Intel
Datasheet
1.NH82801ERSL8WB.pdf
(671 pages)
Specifications of NH82801ERSL8WB
Lead Free Status / RoHS Status
Compliant
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14.2
Intel
®
Table 167. SMBus I/O Register Address Map
82801EB ICH5 / 82801ER ICH5R Datasheet
SMBus I/O Registers
Offset
0Ch
0Dh
00h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Eh
0Fh
10h
14h
16h
17h
11h
HOST_BLOCK_DB
SMLINK_PIN_CTL
SMBUS_PIN_CTL
NOTIFY_DADDR
NOTIFY_DHIGH
NOTIFY_DLOW
XMIT_SLVA
RCV_SLVA
Mnemonic
HST_CMD
SLV_DATA
HST_CNT
AUX_STS
SLV_CMD
HST_STS
AUX_CTL
SLV_STS
HST_D0
HST_D1
PEC
Packet Error Check
Auxiliary Control
Notify Device Address
Notify Data High Byte
Host Status
Host Control
Host Command
Transmit Slave Address
Host Data 0
Host Data 1
Host Block Data Byte
Receive Slave Address
Receive Slave Data
Auxiliary Status
SMLink Pin Control (TCO Compatible
Mode)
SMBus Pin Control
Slave Status
Slave Command
Notify Data Low Byte
Register Name
SMBus Controller Registers (D31:F3)
See register
See register
description
description
Default
0000h
00h
00h
00h
00h
00h
00h
00h
00h
44h
00h
00h
00h
00h
00h
00h
00h
R/WC (special)
R/WC, RO,
R/W, WO
R/W, RO
R/W, RO
R/WC
R/WC
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
521
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