TLE8203EXT Infineon Technologies, TLE8203EXT Datasheet - Page 17
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TLE8203EXT
Manufacturer Part Number
TLE8203EXT
Description
Manufacturer
Infineon Technologies
Datasheet
1.TLE8203EXT.pdf
(33 pages)
Specifications of TLE8203EXT
Operating Temperature (max)
150C
Operating Temperature (min)
-40C
Pin Count
36
Mounting
Surface Mount
Screening Level
Automotive
Lead Free Status / RoHS Status
Supplier Unconfirmed
7.5
Electrical Characteristics: SPI-Timing
V
respect to ground, positive current flowing into pin (unless otherwise specified)
Pos.
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10
7.5.11
7.5.12
1) SPI Timing is not subject to production test - specified by design. SPI functional test is performed at 5 MHz CLK frequency.
Figure 7
7.6
The PWM inputs PWM1 and PWM2 are direct power stage control inputs that can be used to switch on and off
one or more of the power transistors with a PWM signal supplied to this pin. The setting of the SPI Registers
CtrlReg_01 and CtrlReg_11 defines which of the power stages will be controlled by the PWM inputs. If the
selection-bits of power Stage x, xsel1 and xsel2 are LOW, the power stage x is controlled only via the SPI control
bit xON. If the selection bit xsel1 is HIGH and the control bit xON is also high, the power stage x is controlled by
the PWM1 pin (xsel2 and PWM2, respectively). The behavior is shown in the principal schematic and in
below. In terms of power dissipation due to switching loss, a PWM frequency below 200 Hz is recommended.
Final Data Sheet
S
= 8 V to 20 V;
Timing specified with an external load of 30 pF at pin [DO].
Parameter
CSN lead time
CSN lag time
Fall time for CSN, CLK, DI, DO
Rise time for CSN, CLK, DI, DO
DI data setup time
DI data hold time
DI data valid time
DO data setup time
DO data hold time
No-data-time between SPI
commands
Clock frequency
Duty cycle of incoming clock at CLK –
Electrical Characteristics
Timing Diagram
PWM Inputs
V
DD
= 4.75 V to 5.25 V,
T
j
= -40 C to +150 C; INH = High; all outputs open, all voltages with
Symbol
t
t
t
t
t
t
t
t
t
t
f
lead
lag
f
r
SU
h
v
DOsetup
DOhold
nodata
CL
17
Min.
100
100
–
–
40
40
–
0
50
5
–
40
Limit Values
Typ.
–
–
–
–
–
–
–
–
–
–
–
–
Max.
–
–
25
25
–
–
50
60
–
–
2
60
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
%
s
Rev. 1.0, 2009-02-04
Conditions
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
TLE 8203E
Table 5
SPI