ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 504

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.10.2.27 VIP FIFO Address (VIP_FIFO_R_W_ADDR)
VIP Memory Offset 70h
Type
Reset Value
504
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:28
27:16
15:12
11:0
31:9
Bit
Bit
8:0
Name
RSVD
VERT_END
RSVD
VERT_START
Name
RSVD
FIFO_ADDRESS
R/W
00000000h
33234C
Description
Reserved. Set to 0.
Vertical End Capture. This register specifies the last line # in a field/frame that is cap-
tured when the subwindow capture function is enabled in non BT.601 modes. In BT.601
interlaced modes, this register determines when the odd field line capture completes. In
601 non-interlaced modes, this register determines when the video capture completes.
See Figure 6-48 "BT.601 Mode Vertical Timing" on page 470 for additional detail.
Reserved. Set to 0.
Vertical Start Capture. This register specifies the first line # in a field/frame that is cap-
tured when the subwindow capture function is enabled in non 601 modes. In BT.601
interlaced modes, this register determines when the odd field video capture starts. In
BT.601 non-interlaced modes, this register determines when the video capture starts.
See Figure 6-48 "BT.601 Mode Vertical Timing" on page 470 for additional detail.
Description
Reserved. Set to 0.
FIFO ADDRESS. FIFO address for which a FIFO read or write occurs. The data is writ-
ten/read via the FIFO Data register (VIP Memory Offset 74h). Note that the 256x64 bit
FIFO is mapped as a 512x32 bit memory.
VIP_VERT_START_STOP Bit Description
VIP_FIFO_R_W_ADDR Bit Descriptions
VIP_FIFO_R_W_ADDR Register Map
RSVD
AMD Geode™ LX Processors Data Book
Video Input Port Register Descriptions
9
8
7
6
FIFO_ADDRESS
5
4
3
2
1
0