ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 576

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

576
41:40
39:35
34:32
Bit
42
31
30
29
28
27
26
25
Name
SLTO
ILTO
LAT
0 (RO)
PE
BME
TARE
MARE
PS
BMS
TARS
33234C
Description
Subsequent Latency Timeout Select. Specifies the subsequent target latency timeout
limit. If within a burst, the GLPCI module does not respond with the configured number of
clock ticks, the PCI interface will terminate the PCI bus cycle.
0: 8 PCI clock edges
1: 4 PCI clock edges
Initial Latency Timeout Select. Specifies the initial target latency timeout limit for the
PCI interface. If the GLPCI module does not respond with the first data phase within the
configured number of clock edges, the PCI interface will terminate the PCI bus cycle.
If AILTO (MSR 5000201Fh[6]) = 0
If AILTO = 1
PCI Latency Timer. Latency timeout value for limiting bus tenure.
Constant 0 (Read Only). The three least significant bits of the PCI latency timer field are
fixed as zeros. These bits are not used as part of the PCI latency timer comparison.
PCI Error. Allow detection of either a parity error or a system error to be reported in the
PARE bit (MSR 50002003h[21]).
0: Disable.
1: Enable.
Broken Master Error. Allow detection of a broken PCI bus master to be reported in the
BME bit (MSR 50002003h[18]).
0: Disable.
1: Enable.
Target Abort Received Error. Allow reception of a PCI bus target abort to be reported in
the TARE bit (MSR 50002003h[17]).
0: Disable.
1: Enable.
Master Abort Received Error. Allow reception of a PCI bus master abort to be reported
in the MARE bit (MSR 50002003h[16]).
0: Disable.
1: Enable.
PCI ASMI. Allow detection of either a parity error or a system error to be reported in the
PARE bit (MSR 50002002h[21]).
0: Disable.
1: Enable.
Broken Master ASMI. Allow detection of a broken PCI bus master to be reported in the
BME bit (MSR 50002002h[18]).
0: Disable.
1: Enable.
Target Abort Received ASMI. Allow reception of a PCI bus target abort to be reported in
the TARE bit (MSR 50002002h[17]).
0: Disable.
1: Enable.
GLPCI_CTRL Bit Descriptions (Continued)
00: 32 PCI clock edges
01: 16 PCI clock edges
00: 64 PCI clock edges
01: 128 PCI clock edges
10: 8 PCI clock edges
11: 4 PCI clock edges
10: 256 PCI clock edges
11: No timeout
GeodeLink™ PCI Bridge Register Descriptions
AMD Geode™ LX Processors Data Book