ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 62
ALXD800EEXJ2VD
Manufacturer Part Number
ALXD800EEXJ2VD
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.ALXD800EEXJ2VD.pdf
(675 pages)
Specifications of ALXD800EEXJ2VD
Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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4.2.2.3
MSR Address
Type
Reset Value
4.2.2.4
MSR Address
Type
Reset Value
ASMI is a condensed version of the port ASMI signals. The MASK bits can be used to prevent a device from issuing an
ASMI. If the MASK = 1, the device’s ASMI is disabled.
62
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
59:0
Bit
63
62
61
60
Arbitration (ARB)
Asynchronous SMI (ASMI)
Name
QUACK_EN
PIPE_DIS
RSVD
DACK_EN
RSVD
GLIU0: 10000082h
GLIU1: 40000082h
R/W
10000000_00000000h
GLIU0: 10000083h
GLIU1: 40000083h
R/W
00000000_00000000h
33234C
RSVD
Description
Quadruple Acknowledge Enabled. Allow four acknowledgements in a row before
advancing round-robin arbitration. Only applies when arbitrating matching priorities.
0: Disable.
1: Enable.
Pipelined Arbitration Disabled.
0: Pipelined arbitration enabled and GLIU is not limited to one outstanding transaction.
1: Limit the entire GLIU to one outstanding transaction.
Reserved.
Double Acknowledge Enabled. Allow two acknowledgements in a row before advanc-
ing round-robin arbitration. Only applies when arbitrating matching priorities.
0: Disable.
1: Enable.
Reserved.
ARB Bit Descriptions
ASMI Register Map
ARB Register Map
RSVD
RSVD
RSVD
AMD Geode™ LX Processors Data Book
8
8
7
7
GLIU Register Descriptions
6
6
5
5
4
4
3
3
2
2
1
1
0
0
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