QG80333M500 S L8CC Intel, QG80333M500 S L8CC Datasheet - Page 15

• Manufacturer Part Number: QG80333M500 S L8CC
• Manufacturer: Intel

Specifications of QG80333M500 S L8CC

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

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Implication:
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Problem:
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Problem:
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Specification Update
Note: When neither of these are used by the board vendors during manufacturing testing, there is no
Secondary Bus Number register (PEBSBBNR) provides incorrect bus
number
The PCI Express*-to-PCI Bridge Secondary B-Segment Bus Number Register (PEBSBBNR) does
not provide the B-segment bus number. PEBSBBNR is to mirror the Secondary Bus Number
(SCBN) field of the BNUM register (bits[15:8] at offset 18h) in the B-segment configuration
header space. Instead, PEBSBBNR provides the Subordinate Bus Number (SBBN) of the BNUM
register (bits[23:16] at offset 18h) from the A-segment configuration header space.
The I/O processor does not support transactions from the Intel XScale
the B-segment.
To successfully read PCI B-segment devices, software can scan the PCI B-segment configuration
space using configuration reads to determine the bus number.
No
Boundary scan multi-chip module implementation
The 80333 is not BSDL-compliant for the SAMPLE and BYPASS instructions specified by the
JTAG specification 1149.1. It is compliant for most board-level testing. When boards are tested for
opens and shorts, the 80333 BSDL can define the boundary scan length as +1 to encompass the
BYPASS register in the Intel XScale
When doing ID, SAMPLE, or BYPASS, the Intel XScale
path from TDI to TDO one flop longer than the JTAG specification 1149.1 requires, which can
cause canned software to error.
issue.
Intel can provide two BSDL files which allow opens and shorts testing, as long as it does not test
the ID and BYPASS instructions. One BSDL file covers the Intel XScale
other BSDL file covers the I/O processor, with the exception that both instruction sets are reduced
from 14 to 7, since they are operating independently.
No
PCI Express* traffic class (TC) bit[2] ignored for malformed packet checks
PCI Express* Specification, Revision 1.0a Packet formation rules state that Message (Unlock, Slot
Power Limit), I/O, CFG TLP must use Traffic Class 0, such that TC[2:0] of the header field is set
to 000. Receivers that implement the optional Malformed Packet Check must check for TC usage.
The 80333 checks only TC[1:0] and ignores bit[2].
Packet formation violations are not detected and flagged as Malformed Packets.
None
No
This was originally written with the understanding that malformed packet checks using TC[2:0]
were required. It is now understood that the PCI Express* to PCI/PCI-X bridge Specification 1.0
requires PCI Express* bridges to ignore TC and forward all requests regardless of TC labeling. In
order to comply with the PCI Express* to PCI/PCI-X bridge Specification 1.0, TC checks are to be
removed.
Fix. Not to be fixed. See the
Fix. Not to be fixed. See the
Fix. See the
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
®
processor (therefore not visible).
®
processor BYPASS register makes the
7.
Intel® 80333 I/O Processor
®
processor on A-segment to
®
processor unit, and the
7.
7.
Non-Core Errata
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