QG80333M500 S L8CC Intel, QG80333M500 S L8CC Datasheet - Page 24

• Manufacturer Part Number: QG80333M500 S L8CC
• Manufacturer: Intel

Specifications of QG80333M500 S L8CC

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Intel® 80333 I/O Processor
Non-Core Errata
30.
Problem:
Implication:
Workaround:
Status:
31.
Problem:
Implication:
Workaround:
Status:
24
Note: Only the DMA can generate a 64-bit address (DAC) on the internal bus.
Note: Use of the DMA to generate the transaction would require not only the modification of the
Bus Interface Unit (BIU) claims DAC addresses in the range of the Memory
Mapped Registers (MMR)
The BIU incorrectly decodes and claims Dual Address Cycle (DAC) addresses in the
xxxx_xxxx_FFFF_E000h to xxxx_xxxx_FFFF_FFFFh range (e.g. - ‘x’ represents any bit being set
to ‘1’). The 32-bit address range of FFFF_E000h to FFFF_FFFFh on the internal bus, represents
MMR and reserved space. When a 64-bit address in this range is presented on the internal bus,
multiple internal bus units, one of them being the BIU, will claim the transaction.
Using DAC addresses in the xxxx_xxxx_FFFF_E000h to xxxx_xxxx_FFFF_FFFFh range on the
internal bus will cause an internal bus conflict that may result in the reception of undesired data and
setting of error flags.
Avoid
xxxx_xxxx_FFFF_FFFFh range. This can be done by utilizing one of the two 64MB ATU
outbound memory windows (8000 0000H or 8400 0000H) and its corresponding outbound
translation registers (OMWTVR0/OUMWTR0 or OMWTVR1/OUMWTR1) in order to present a
32 bit address on the internal bus and generate a 64 bit address on the PCI bus.
The upper translate value register should be programmed with the upper 32 bits of the desired PCI
address. The lower translate value register would then be configured to OR in the appropriate
value such that the desired lower 32 bits appear on the PCI bus after translation. Refer to Section
3.2.2 “Outbound Transactions – Single Address Cycle (SAC) Internal Bus Transactions” in the
Intel® 80333 I/O Processor Developer’s Manual for more information on how the windowing and
translation scheme works.
It is possible to now generate the 32 bit internal bus transaction either using the core or the DMA.
Both options are viable and one may be preferable over the other depending on the application.
descriptors in question and setting of the memory-memory transfer enable bit (DCRx) for those
descriptors, but care must also be taken not to allow any individual transfer to overrun the size of
the outbound window (64MB).
No
Tc1(min) of the PCI-X clock observed to be marginally less than the
requirement specified for the PCI-X (Mode 1, class1) clock jitter.
The 80333 generates the PCI-X clock with a nominal frequency of 133 MHz (Tc1 of 7.5 ns). After
considering the clock jitter, the minimum clock period (Tc1(min)) observed at the pin may be less
than 7.5 ns. The PCI-X class 1 clock jitter specification for mode 1 requires the Tcyc-min to be 7.5
ns with jitter consideration. The same applies for the PCI-X clock generated @ 66 MHz.
No negative impact is expected, when compliant with the routing guidelines.
There is no workaround to adjust the minimum clock period (Tc1(min)) of the PCI-X clocks.
However, the routing guidelines for the PCI-X clock signal take into consideration the effect of the
jitter on the minimum clock period (Tc1(min)). Conforming to the routing guidelines in the 80333
design guide will offset the effect of the marginally reduced minimum clock period (Tc1(min))
towards the setup and hold times. Therefore, for system boards that are compliant with the routing
guidelines, the risk of violating the setup and hold time requirements and any resulting functional
impact, is low. Please refer to the 80333 I/O processor design guide (305434) for further
information on the PCI-X clock routing guidelines.
No
Fix. Not to be fixed. See the
Fix. Not to be fixed. See the
using
the
DMA
with
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
DAC
addresses
in
the
xxxx_xxxx_FFFF_E000h
Specification Update
7.
7.
to