QG80333M500 S L8CC Intel, QG80333M500 S L8CC Datasheet - Page 35

• Manufacturer Part Number: QG80333M500 S L8CC
• Manufacturer: Intel

Specifications of QG80333M500 S L8CC

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

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Specification Update
Note: Access to the bridge configuration header space is done by using a configuration cycle, which is
generated by the ATU OCCAR and OCCDR registers.
No
Write requirements for the Peripheral Bus Interface
PBI write requirements are as follows:
The data presented must not be larger than the PBI width.
Every PBI device must be mapped in the MMU the same way. Making the device address space
cacheable can result in buffered/coalesced writes, which are burst to the PBI.
XCB = 000 and XCB = 101 are the only cache policies that can be used for PBI. All other cache
policies result in multi-byte transactions.
No
PCI-X Status Register during PCI mode
The PCI-X Status Register (PX_SR, offset E4h-E5h) in the ATU has meaning only in PCI-X mode.
The device number and bus number fields are always updated when a configuration write is
detected. The ATU always grabs AD[15:11] for configuration writes, whether it is in PCI or PCI-X
mode. When a PCI configuration transaction occurs, the Device Number bits[7:3] are updated to a
value of 00000b from the default value of 11111b. The bus number bits[15:8] are grabbed only
during the attribute phase (which does not exist for PCI).
No
M_RST# driven to DDR-II or DDR-I voltage levels
The de-asserted voltage level on M_RST# with DDR-II is 1.8 V and with DDR-I is 2.5 V. When
M_RST# is needed for other devices (for example, Flash), make sure these voltage levels are
appropriate for the target device.
No
BIU master abort causes two interrupts on reads
The Bus Interface Unit (BIU) will generate an interrupt when the BIU gets master aborted on an
internal bus write. The functionality is different between a read and write case. For a write, the BIU
master abort asserts IINTSRC[29] (when enabled) and does not assert an error to the core. For a
read, the BIU master abort asserts both IINTSRC[29] (when enabled) and an error to the core.
Therefore, on a read case two interrupts is generated. When the interrupt source is masked, then
only the master abort on reads is detected, and this is from the direct core error.
No
4. Clear (restore) the Bus Master Enable bit for the ATU in ATUCMD[2] (offset 04h).
5. Clear the ATU retry bit in PCSR[2] (offset 84h).
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Fix. See the
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The Flash or memory must be set up to accept writes.
Each write must be checked to make sure it has completed, before the next write can start.
It is now allowed to burst writes to the PBI.
f. Restore the A-bridge command register and clear the A-bridge retry bit in BINIT[3]
(offset FCh).
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
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Specification Clarifications
Intel® 80333 I/O Processor
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