QG80333M500 S L8CC Intel, QG80333M500 S L8CC Datasheet - Page 19

• Manufacturer Part Number: QG80333M500 S L8CC
• Manufacturer: Intel

Specifications of QG80333M500 S L8CC

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

15.
Problem:
Implication:
Workaround:
Status:
16.
Problem:
Implication:
Workaround:
Status:
17.
Problem:
Implication:
Workaround:
Status:
18.
Problem:
Implication:
Workaround:
Specification Update
IOAPIC End of Interrupt (EOI) Register is Read-Write, should be Write-Only
IOAPIC End of Interrupt register (APIC_EOI, offset 40h) should be write-only. The APIC
specification specifies that this register be implemented as write-only. This register was
inadvertently implemented as read-write.
When implemented as write-only, this register returns FFh when read. Since this register is
implemented as read-write, the 80333 returns the “real” value of the register contents when read.
No negative impact expected.
None
No
Unreliable PCI Express* link operation when L0s active state power
management is enabled
PCI Express* link operation is unreliable after the L0s state is enabled in the 80333.
When L0s is enabled, the system hangs and other system instability occurs.
None
No
not supported in the 80333” on page
Hub BIOS Specification Update for details on how to disable L0s support. See the
“Summary Table of Changes” on page
SSE bit set for PERR# assertion when error reporting is masked
During a downstream memory write to the 80333, the following erroneous behavior is seen when
PERR# is asserted on the secondary bus:
False indication of an error message escalated as recorded in SSE of the PSTS register being set.
This is considered low risk since the escalation of the message is functioning properly.
None
No
Data Parity Error detected on PCI/X interface fails to propagate bad parity
In PCI and PCI-X mode using 32-bit data transfers, when a read request is disconnected at an even
DWORD boundary with data parity error, such that the subsequent request for partial data gets
retried, the completion for this request is issued over PCI Express* to the MCH (root complex)
without the poisoned data EP field set in the PCI Express* TLP header.
Corrupted data forwarded without error indication when error escalation is not enabled.
Uncorrectable error escalation must be enabled in the MCH and the 80333 to contain this data
parity escape. Therefore, a complete workaround for this erratum also includes MCH/root complex
specific BIOS updates. Refer to the latest version of the Intel
Specification Update for details on this workaround.
•
•
•
Fix. Not to be fixed. See the
Fix. Not to be fixed. See the
Fix. Not to be fixed. Refer to Specification Clarification
Signaled System Error (SSE) in the PSTS register (D:0, F:0 and 2, offset 06h, bit[14]) is set
when SERR# Enable (SEE) (D:0, F:0 and 2, offset 04h, bit[8]) and Parity Error Response
Enable (PERE) (D:0, F:0 and 2, offset 04h, bit[6]) are set in the PCICMD register.
The PERE bit in the BCTRL register is set (D:0, F:0 and 2, offset 3Eh, bit[0]).
Error reporting is disabled in the PCIXERRUNC_MSK register (D:0, F:0 and 2, offset 130h).
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
43) and the latest version of the Intel
7.
36 (“PCI Express* L0s functionality
®
6700PXH 64-bit PCI Hub BIOS
Intel® 80333 I/O Processor
®
6700PXH 64-bit PCI
7.
7.
Non-Core Errata
Table ,
19