QG80333M500 S L8CC Intel, QG80333M500 S L8CC Datasheet - Page 39

• Manufacturer Part Number: QG80333M500 S L8CC
• Manufacturer: Intel

Specifications of QG80333M500 S L8CC

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

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Specification Update
Note: Single-byte transactions on 16-bit PBI bus is not a supported case. Also, a PBI bus configured as
No
UART, I
32-bit accesses
The UART, I
enables. Due to this functionality, accessing any of these unit memory-mapped registers (MMR)
with any accesses less than 32-bits can result in corruption of the other bits in the 32-bit MMR. For
example, the GPOD register (located at FFFF_F788h) implements functionality for bit[10] and
bit[11]. When software performs a byte access to GPOD, this could cause bit[10] and bit[11] to be
written with incorrect data.
While most of these registers implement only the lower 8 bits (the upper three bytes are
“reserved”), the recommendation is that all UART, I
32-bit registers. While it is desired that 32-bit accesses be performed, it is acceptable to access with
less than 32 bits, as long as all non-reserved bits are accessed. For purposes of future expansion,
32-bit accesses are preferred.
No
UART Interrupt Identification Register
The UART Interrupt Identification Register (UxIIR) is read by software to determine the type and
source of UART interrupts. This register gathers and priority encodes the various sources of UART
interrupts. The register is read after an interrupt occurs. Enabling and disabling of interrupts (via
the Interrupt Enable Register [UxIER] or the Modem Control Register [UxMCR]) affects whether
or not the interrupt to the processor occurs. This does not effect the logging of the status of what is
happening in the UART. The UART operates in interrupt or polling mode. In polling mode, all
interrupts to the processor are disabled.
No
Reads on 16-bit PBI bus operate as 32-bit
Two-byte and four-byte read transactions on the Peripheral Bus Interface (PBI) bus operate as burst
reads (in other words, two 16-bit read cycles). All the read transactions from the Intel XScale
processor to PBI devices (such as SRAM, flash, and so on) are translated to burst reads with burst
size of 2, even though there is no necessity to generate a burst transaction. Therefore, devices on
the 16-bit PBI bus must be configured as pre-fetchable.
8-bit does not operate this way.
No
3.3 V to 1.5 V leakage
There is a leakage path from the 3.3 V rail to the 1.5 V rail. When the 3.3 V is powered-on and the
1.5 V is not, then ~500 mV is seen on the 1.5 V rail. This leakage is expected and does not cause
any long-term reliability issues.
For related issues, see Non-Core Erratum
edge of PWRGD” on page
No
Fix. See the
Fix. See the
Fix. See the
Fix. See the
Fix. See the
ldmfd
2
C and GPIO memory mapped registers should be addressed with
2
C and GPIO units sit on a dedicated low-speed internal bus that does not support byte
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
sp!,{r4, fp, ip, pc}
17).
10 (“Secondary bus PCI RST# pulse prior to the rising
2
C, and GPIO MMRs must be accessed only as
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Specification Clarifications
Intel® 80333 I/O Processor
39
®