QG80333M500 S L8CC Intel, QG80333M500 S L8CC Datasheet - Page 43

• Manufacturer Part Number: QG80333M500 S L8CC
• Manufacturer: Intel

Specifications of QG80333M500 S L8CC

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

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Specification Update
PWRDELAY needs only a pull-up for battery back-up mode
The I
circuit to be simplified to a single pull-up resistor, to enable battery back-up mode. PWRDELAY
must be isolated from all other circuitry, and only a 1.5 KΩ pull-up to 3.3 V is required. When
battery back-up is not required, PWRDELAY must have a 1.5 KΩ pull-down resistor.
No
PCI Express* L0s functionality not supported in the 80333
Due to the unreliable behavior described in Non-core Erratum
operation when L0s active state power management is enabled” on page
management state is not supported. The BIOS must be updated to leave L0s disabled on the 80333
by default, and eliminate any setup option with which to enable it. Additionally, the BIOS must not
allow L0s to be enabled on any PCI Express* root ports connected to the 80333 end-devices.
No
DDRRES2 can be pulled down to reduce current during self-refresh
DDRRES2 is used as compensation for DDR-II OCD. Since OCD is not supported in the 80333
(see Specification Clarification 34,
page
No
DDRSLWCRES resistor values
The following resistors can be used on DDRSLWCRES:
No
B_PME# routing recommendation when using Parallel Hot Plug 1-slot,
no-glue mode
When the B-segment is in parallel hot plug, one-slot, no-glue mode, the B_PME# signal might be
pulled to ground. Since B_PME# is active low and might be connected to the GIPx pin of ICHx,
the ICHx interprets the low voltage of B_PME# as a power-management event from the PCI-X
slot. This might cause the system not to remain in the appropriate power mode when no add-in card
is plugged into the slot. B_PME# must be high when there is no PME request from the PCI-X slot.
To work around this issue, add a diode between the buffer and the 80333, and add a 1 KΩ–10 KΩ
pull-up resistor to the B_PME# signal. The diode can prevent ICHx from getting a B_PME# low
logic level when there is no PME request from the PCI-X slot.
No
•
•
Fix. See the
Fix. See the
Fix. See the
Fix. See the
Fix. See the
DDR-I memory: 845 Ω or 1.13 KΩ resistor, 1%
DDR-II memory: 825 Ω or 976 Ω resistor, 1%
42), DDRRES2 can be pulled down to reduce current draw during self-refresh mode.
2
C bus is no longer included in the processor reset equation. This allows the PWRDELAY
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
“OCD and Receive Enable calibration de-featured” on
7.
7.
7.
7.
7.
16 (“Unreliable PCI Express* link
Specification Clarifications
Intel® 80333 I/O Processor
19), L0s active power
43