PSB21373HV1.1XT Infineon Technologies, PSB21373HV1.1XT Datasheet - Page 87
PSB21373HV1.1XT
Manufacturer Part Number
PSB21373HV1.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PSB21373HV1.1XT.pdf
(242 pages)
Specifications of PSB21373HV1.1XT
Lead Free Status / RoHS Status
Compliant
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Data Sheet
the microcontroller as master. The control of the data transfer between the CPU and the
HDLC controller is handled via interrupts (HDLC controller
(Host
There are three different interrupt indications in the ISTAH register concerned with the
reception of data:
– RPF (Receive Pool Full) interrupt, indicating that a data block of the selected length
– RME (Receive Message End) interrupt, indicating that the reception of one message
– RFO (Receive Frame Overflow) interrupt, indicating that a complete frame could not
There are two control commands (bits of CMDR) that are used with the reception of data:
– RMC (Receive Message Complete) command, telling the HDLC controller that a data
– RRES (Receiver Reset) command, resetting the HDLC receiver and clearing the
(EXMR.RFBS) can be read from RFIFO. The message which is currently received
exceeds the block size so further blocks will be received to complete the message.
is completed, i.e. either
• a short message is received
• the last part of a long message is received
be stored in RFIFO and is therefore lost as the RFIFO is occupied. This occurs if the
host fails to respond quickly enough to RPF/RME interrupts since previous data was
not read by the host.
block has been read from the RFIFO and the corresponding FIFO space can be
released for new receive data.
receive FIFO of any data (e.g. used before start of reception). It has to be used after
having changed the mode.
(message length
(message length
and is stored in the RFIFO.
HDLC controller).
the defined block size (EXMR.RFBS) or
the defined block size (EXMR.RFBS))
87
Host) and commands
PSB 21373
2002-05-13
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