ML610Q422-NNNTBZ03A7 Rohm Semiconductor, ML610Q422-NNNTBZ03A7 Datasheet - Page 202

• Manufacturer Part Number: ML610Q422-NNNTBZ03A7
• Description: MCU 8BIT 32K FLASH 22CH 120-TQFP
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of ML610Q422-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 4.2MHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 100-TFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ML610Q421/ML610Q422 User’s Manual
Chapter 14 UART
14.3.4
Transmit Operation
Transmission is started by setting the U0IO bit of the UART0 mode register 0 (UA0MOD0) to “0” to select transmit
mode and setting the U0EN bit of the UART0 control register (UA0CON) to “1”.
Figure 14-5 shows the operation timing for transmission.
When the U0EN bit is set to “1” (1), the baud rate generator generates an internal transfer clock of the baud rate set
and starts transmission.
The start bit is output to the TXD0 pin by the falling edge of the internal transfer clock (2). Subsequently, transmit
data, a parity bit, and a stop bit are output.
When the start bit is output (2), a UART0 interrupt is requested. In the UART0 interrupt routine, the next data to be
transmitted is written to the transmit/receive buffer (UA0BUF).
When the next data to be transmitted is written to the transmit/receive buffer (UA0OBUF), the transmit buffer status
flag (U0FUL) is set to “1” (3) and a UART0 interrupt is requested on the falling edge of the internal transfer clock (4)
after transmission of the stop bit. If the UART0 interrupt routine is terminated without writing the next data to the
transmit/receive buffer, the U0FUL bit is not set to “1” (5) and transmission continues up to the transmission of the
stop bit, then the U0EN bit is reset to “0” and a UART0 interrupt is requested.
The valid period for the next transmit data to be written to the transmit/receive buffer is from the generation of an
interrupt to the termination of stop bit transmission. (6)
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