ML610Q422-NNNTBZ03A7 Rohm Semiconductor, ML610Q422-NNNTBZ03A7 Datasheet - Page 60

• Manufacturer Part Number: ML610Q422-NNNTBZ03A7
• Description: MCU 8BIT 32K FLASH 22CH 120-TQFP
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of ML610Q422-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 4.2MHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 100-TFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.3.3.3
• If the ELEVEL bit is 0H, it indicates that the CPU is performing neither nonmaskable interrupt processing nor maskable
• If the ELEVEL bit is 1H, it indicates that the CPU is performing maskable interrupt processing or software interrupt
• If the ELEVEL bit is 2H, it indicates that the CPU is performing non-maskable interrupt processing. (ELEVEL is set
• If the ELEVEL bit is 3H, it indicates that the CPU is performing interrupt processing specific to the emulator. This
The operation of returning from the STOP mode and HALT mode varies according to the interrupt level (ELEVEL) of the
program status word (PSW), master interrupt enable flag (MIE), the contents of the interrupt enable register (IE0 to IE3),
and whether the interrupt is a non-maskable interrupt or a maskable interrupt.
For details of PSW and the IE and IRQ registers, see “nX-U8/100 Core Instruction Manual” and Chapter 5, “Interrupt”,
respectively.
Table 4-1 and Table 4-2 show the return operations from STOP/HALT mode.
Notes:
interrupt processing nor software interrupt processing.
processing. (ELEVEL is set during interrupt transition cycle.)
during interrupt transition cycle.)
setting is not allowed in normal applications.
ELEVEL
ELEVEL
0, 1, 2
0, 1
2,3
3
*
*
*
*
Note on Return Operation from STOP/HALT Mode
Table 4-1 Return Operation from STOP/HALT Mode (Non-Maskable Interrupt)
Table 4-2 Return Operation from STOP/HALT Mode (Maskable Interrupt)
MIE
MIE
0
1
1
*
*
*
*
*
IEn.m
IEn.m
−
−
−
0
1
1
1
*
IRQn.m
IRQn.m
0
1
1
0
1
1
1
1
Not returned from STOP/HALT mode.
After the mode is returned from STOP/HALT mode, the program
operation restarts from the instruction following the instruction that
sets the STP/HLT bit to “1”. T he program operation does not go to the
interrupt routine.
After the mode is returned from the STOP/HALT mode, program
operation restarts from the instruction following the instruction that
sets the STP/HLT bit to “1”, then goes to the interrupt routine.
Not returned from STOP/HALT mode.
After the mode is returned from STOP/HALT mode, the program
operation restarts from the instruction following the instruction that
sets the STP/HLT bit to “1”. T he program operation does not go to the
interrupt routine.
After the mode is returned from the STOP/HALT mode, program
operation restarts from the instruction following the instruction that
sets the STP/HLT bit to “1”, then goes to the interrupt routine.
4 – 14
Return operation from ST OP/HALT mode
Return operation from ST OP/HALT mode
ML610Q421/ML610Q422 User’s Manual
Chapter 4 MCU Control Function