ML610Q422-NNNTBZ03A7 Rohm Semiconductor, ML610Q422-NNNTBZ03A7 Datasheet - Page 310
ML610Q422-NNNTBZ03A7
Manufacturer Part Number
ML610Q422-NNNTBZ03A7
Description
MCU 8BIT 32K FLASH 22CH 120-TQFP
Manufacturer
Rohm Semiconductor
Series
-r
Datasheets
1.ML610Q482P-NNNTB03A7.pdf
(20 pages)
2.ML610Q421P-NNNTB03A7.pdf
(35 pages)
3.ML610Q421P-NNNTB03A7.pdf
(426 pages)
Specifications of ML610Q422-NNNTBZ03A7
Core Processor
nX-U8/100
Core Size
8-Bit
Speed
4.2MHz
Connectivity
I²C, SSP, UART/USART
Peripherals
LCD, Melody Driver, POR, PWM, WDT
Number Of I /o
14
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 2x12b, 2x24b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
100-TFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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(2) Operation in Counter B reference mode
Figure 24-7 shows the operation timing in Counter B reference mode.
Following is an example of operation procedure in Counter B reference mode:
When the RARUN bit is set to “1” and the RCON signal (signal synchronized with the fall of the base clock) is set
to”1”, the RC oscillator circuit starts operation and Counter B starts counting of the RC oscillator clock (RCCLK).
When Counter B overflows, the RARUN bit is automatically reset (6) and conversion operation terminates. At the
same time, an RC-ADC interrupt request (RADINT) occurs. (7)
When the RCON signal is set to “1”, Counter A starts counting of the base clock (BSCLK). When the RARUN bit is
reset due to overflow of Counter B, Counter A stops counting.
The final count “nA1” of Counter A is the CLK count value during the gate time “nB1 t
following expression:
That is, “nA1” is a value inversely proportional to the RC oscillation frequency f
Preset to Counter B (RADCB2–0) the value obtained by subtracting the count value “nB1” from the maximum
value + 1 (1000000H). The product of the count value “nB1” and the RCCLKclock period indicates the gate
time.
Preset “000000H” to Counter A (RADCA2–0).
Set the OM3–OM0 bits of RADMOD to desired oscillation mode (see Table 24-1).
Set the RADI bit of RADMOD to “1” to specify generating of an interrupt request signal by Counter B overflow.
Set the RARUN bit of RADCON to “1” to start A/D conversion.
nA1
≅
nB1•
t
t
RCCLK
BSCLK
∝
24 – 14
f
RCCLK
1
Chapter 24 RC Oscillation Type A/D Converter
ML610Q421/ML610Q422 User’s Manual
RCCLK
.
RCCLK
” and is expressed by the
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