ML610Q408-NNNTBZ03A7 Rohm Semiconductor, ML610Q408-NNNTBZ03A7 Datasheet - Page 87
ML610Q408-NNNTBZ03A7
Manufacturer Part Number
ML610Q408-NNNTBZ03A7
Description
MCU 8BIT 16K FLASH 8CH 100-TQFP
Manufacturer
Rohm Semiconductor
Series
-r
Datasheets
1.ML610Q482P-NNNTB03A7.pdf
(20 pages)
2.ML610Q407P-NNNTB03A7.pdf
(33 pages)
3.ML610Q407P-NNNTB03A7.pdf
(391 pages)
Specifications of ML610Q408-NNNTBZ03A7
Core Processor
nX-U8/100
Core Size
8-Bit
Speed
2MHz
Connectivity
SSP, UART/USART
Peripherals
LCD, Melody Driver, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.25 V ~ 3.6 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
100-TFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ML610Q408-NNNTBZ03A7
Manufacturer:
Rohm Semiconductor
Quantity:
10 000
- ML610Q482P-NNNTB03A7 PDF datasheet
- ML610Q407P-NNNTB03A7 PDF datasheet #2
- ML610Q407P-NNNTB03A7 PDF datasheet #3
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- Download datasheet (2Mb)
6. Clock Generation Circuit
6.1 Overview
6.1.1
6.1.2
The clock generation circuit generates and provides a low-speed clock (LSCLK), the low-speed double clock (LSCLK x
2), a high-speed clock (HSCLK), a system clock (SYSCLK), and a high-speed output clock (OUTCLK). LSCLK,
LSCLK x 2, and HSCLK are time base clocks for the peripheral circuits, SYSCLK is a basic operation clock of CPU,
and OUTCLK is a clock that is output from a port.
For the OUTCLK output port, see Chapter 15, “Port 2”.
For the STOP mode described in this chapter, see Chapter 4, "MCU Control Function."
Figure 6-1 shows the configuration of the clock generation circuit.
Note:
This LSI starts operation with the low-speed clock after power-on or a system reset. At initialization by software, set the
FCON0 or FCON1 register to switch the clock to a required one. Operation of this LSI is not guaranteed under a
condition where a low-speed clock is not supplied.
• Low-Speed Clock Generation Circuit: 32.768kHz crystal oscillation mode
• High-speed clock generation circuit
Features
Configuration
FCON0 : Frequency control register 0
FCON1 : Frequency control register 1
- Capable of using the 32.768kHz double clock LSCLK x 2 (64kHz) for some peripherals
- 500kHz/2MHz RC oscillation mode
500kHz or 2MHz RC oscillation
XT0
XT1
High-speed clock
generation circuit
Low-Speed Clock
generation circuit
Figure 6-1 Configuration of Clock Generation Circuit
OSCLK
FCON0,FCON1
Dividing selection
Dividing selection
1/1,1/2,1/4,1/8
1/1,1/2,1/4,1/8
6-1
ML610Q407/ML610Q408/ML610Q409 User's Manual
Chapter 6 Clock Generation Circuit
System clock
(SYSCLK)
High-speed clock
(HSCLK)
High-speed output clock
(OUTCLK)
Low-speed double clock
(LSCLK x 2)
Low-speed clock
(LSCLK)
Data bus
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