ML610Q408-NNNTBZ03A7 Rohm Semiconductor, ML610Q408-NNNTBZ03A7 Datasheet - Page 89

• Manufacturer Part Number: ML610Q408-NNNTBZ03A7
• Description: MCU 8BIT 16K FLASH 8CH 100-TQFP
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of ML610Q408-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.25 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 100-TFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.2.2
Address: 0F002H
Access: R/W
Access size: 8/16 bit
Initial value: 33H
FCON0 is a special function register (SFR) to control the high-speed clock generation circuit and to select system clock.
[Description of Bits]
Note:
Internal logic voltage (V
500kHz oscillation is selected. V
Ensure to write this bit when the high-speed clock oscillator circuit stops oscillating (During FCON1 register's ENOSC
bit is "0").
Initial value
•
•
•
FCON0
Frequency Control Register 0 (FCON0)
R/W
SYSC1, SYSC0 (bits 1, 0)
At system reset, 1/8OSCLK is selected.
OUTC1, OUTC0 (bits 5, 4)
OSCM2 (bit 6)
The SYSC1 and SYSC0 bits are used to select the frequency of the high-speed clock (HSCLK) used for system
clock and peripheral circuits (including high-speed time base counter). OSCLK, 1/2OSCLK, 1/4OSCLK, or
1/8OSCLK can be selected. The maximum operating frequency guaranteed for the system clock (SYSCLK) of
this LSI is 500 kHz or 2 MHz.
The OUTC1 and OUTC0 bits are used to select the frequency of the high-speed output clock which is output
when the secondary function of the port is used. OSCLK, 1/2OSCLK, 1/4OSCLK, or 1/8OSCLK can be
selected.
At system reset, 1/8OSCLK is selected.
This bit sets the high-speed clock oscillation frequency. 500kHz or 2MHz can be selected. This bit can be
written only when the high-speed clock oscillator circuit stops oscillating (During FCON1 register's ENOSC bit
is "0").
SYSC1
OUTC1
0
0
1
1
0
0
1
1
OSCM2
R/W
—
7
0
0
1
SYSC0
OUTC0
0
1
0
1
DDL
0
1
0
1
OSCM2
) is changed by OSCM2 bit. V
500kHz oscillation (initial value)
2MHz oscillation
R/W
6
0
OSCLK
1/2OSCLK
1/4OSCLK
1/8OSCLK (initial value)
DDL
OSCLK
1/2OSCLK
1/4OSCLK
1/8OSCLK (initial value)
becomes Typ.1.5V when OSCM2 is set to “1” and 2MHz oscillation is selected. .
OUTC1
R/W
5
1
OUTC0
6-3
R/W
4
1
Description
ML610Q407/ML610Q408/ML610Q409 User's Manual
DDL
Description
becomes Typ.1.2V when OSCM2 is set to “0” and
Description
R/W
—
3
0
Chapter 6 Clock Generation Circuit
R/W
—
2
0
SYSC1
R/W
1
1
SYSC0
R/W
0
1