MM74HC4046N Fairchild Semiconductor, MM74HC4046N Datasheet - Page 8

• Manufacturer Part Number: MM74HC4046N
• Description: IC LOCK LOOP PHASE CMOS 16-DIP
• Manufacturer: Fairchild Semiconductor
• Series: 74HCr
• Type: Phase Lock Loop (PLL)r

Specifications of MM74HC4046N

• Pll: No
• Input: CMOS
• Output: 3-State
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 14MHz
• Divider/multiplier: No/No
• Voltage - Supply: 2 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Frequency-max: 14MHz
• Supply Voltage (max): 6 V
• Supply Voltage (min): 2 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: Through Hole
• Operating Supply Voltage: 2.5 V, 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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•Given: f
•Use f
Detailed Circuit Description
VOLTAGE CONTROLLED OSCILLATOR/SOURCE
FOLLOWER
The VCO requires two or three external components to
operate. These are R1, R2, C1. Resistor R1 and capacitor
C1 are selected to determine the center frequency of the
VCO. R1 controls the lock range. As R1’s resistance
decreases the range of f
VCO’s gain decreases. As C1 is changed the offset (if
used) of R2, and the center frequency is changed. (See
typical performance curves) R2 can be used to set the off-
set frequency with 0V at VCO input. If R2 is omitted the
VCO range is from 0Hz. As R2 is decreased the offset fre-
quency is increased. The effect of R2 is shown in the
design information table and typical performance curves.
center frequency vs R1, C
to determine R1 and C1
0
with curve titled
0
R
2
VCO WITHOUT OFFSET
Comparator I
R2 =
min
to f
•Given: f
•Calculate f
•Use f
•Calculate f
•Use f
equation f
offset frequency vs R2, C
to determine R2 and C1
the equation f
f
titled f
to determine ratio R2/R1
to obtain R1
o
max
f
L
min
max
/f
increases. Thus the
max
o
0
/f
and f
with curve titled
min
/f
min
min
max
f
min
L
R
2
with curve
L
/f
max
from the
vs R2/R1
min
f
o
/f
from
min
f
L
FIGURE 1.
8
•Given: f
•Calculate f
•Use f
By increasing the value of R2 the lock range of the PLL is
offset above 0Hz and the gain (Volts/rad.) does not
change. In general, when offset is desired, R2 and C1
should be chosen first, and then R1 should be chosen to
obtain the proper center frequency.
Internally the resistors set a current in a current mirror as
shown in Figure 1. The mirrored current drives one side of
the capacitor once the capacitor charges up to the thresh-
old of the schmitt trigger the oscillator logic flips the capaci-
tor over and causes the mirror to charge the opposite side
of the capacitor. The output from the internal logic is then
taken to pin 4.
equation f
center frequency vs R1, C
to determine R1 and C1
0
with curve titled
max
o
0
R
from the
2
f
max
VCO WITHOUT OFFSET
/2
Comparator II & III
•Given: f
•Use f
•Calculate f
•Use f
offset frequency vs R2,
C to determine R2 and C1
titled f
to determine ratio R2/R1
to obtain R1
min
max
max
min
with curve titled
/f
/f
min
max
min
and f
R
2
with curve
/f
vs R2/R1
min
max