CD4541BCN Fairchild Semiconductor, CD4541BCN Datasheet - Page 2
![IC TIMER PROGRAMMABLE 14-DIP](/photos/6/57/65733/261-14-dip_sml.jpg)
CD4541BCN
Manufacturer Part Number
CD4541BCN
Description
IC TIMER PROGRAMMABLE 14-DIP
Manufacturer
Fairchild Semiconductor
Type
Programmable Timerr
Datasheet
1.CD4541BCM_Q.pdf
(8 pages)
Specifications of CD4541BCN
Frequency
100kHz
Voltage - Supply
3 V ~ 15 V
Operating Temperature
-55°C ~ 125°C
Package / Case
14-DIP (0.300", 7.62mm)
Number Of Internal Timers
1
Supply Voltage (max)
3 V to 15 V
Supply Voltage (min)
3 V
Maximum Power Dissipation
700 mW
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 55 C
Mounting Style
Through Hole
Propagation Delay (max)
8000 ns @ 5 V or 3000 ns @ 10 V or 2000 ns @ 15 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Count
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
4541
4541B
4541B
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CD4541BCN
Manufacturer:
FAIRCHILD
Quantity:
100
Part Number:
CD4541BCN
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
www.fairchildsemi.com
Truth Table
Operating Characteristics
With Auto Reset pin set to a “0” the counter circuit is initial-
ized by turning on power. Or with power already on, the
counter circuit is reset when the Master Reset pin is set to
a “1”. Both types of reset will result in synchronously reset-
ting all counter stages independent of counter state.
The RC oscillator frequency is determined by the external
RC network, i.e.:
and R
The time select inputs (A and B) provide a two-bit address
to output any one of four counter stages (2
2
represent the Q output of the Nth stage of the counter.
When A is “1”, 2
Solid Line
Dashed Line
16
Pin
10
5
6
9
). The 2
S
Auto Reset Operating
Timer Operational
Output Initially Low
after Reset
Single Cycle Mode
2 R
R
f
TC
n
R
f
tc
10.2 kHz @ V
TC
counts as shown in the Division Ratio Table
56 k , R
7.75 kHz @ V
where R
16
56 k , R
Typical RC Oscillator
is selected for both states of B.
0
Characteristics
S
S
DD
S
1 k
DD
120 k
10 k
10V and T
and C
10V and T
State
and C
Auto Reset Disabled
Master Reset On
Output Initially High
after Reset
Recycle Mode
1000 pF
A
A
25
1000 pF
25
8
, 2
1
10
, 2
13
, and
2
Division Ratio Table
However, when B is “0”, normal counting is interrupted and
the 9th counter stage receives its clock directly from the
oscillator (i.e., effectively outputting 2
The Q/Q select output control pin provides for a choice of
output level. When the counter is in a reset condition and
Q/Q select pin is set to a “0” the Q output is a “0”. Corre-
spondingly, when Q/Q select pin is set to a “1” the Q output
is a “1”.
When the mode control pin is set to a “1”, the selected
count is continually transmitted to the output. But, with
mode pin “0” and after a reset condition the RS flip-flop
resets (see Logic Diagram), counting commences and after
2
change state. Hence, after another 2
will not change. Thus, a Master Reset pulse must be
applied or a change in the mode pin level is required to
reset the single cycle operation.
Line A: f as a function of C and (R
Line B: f as a function of R
n 1
counts the RS flip-flop sets which causes the output to
A
0
0
1
1
RC Oscillator Frequency as a
B
0
1
0
1
Function of R
TC
and (C
Counter Stages
TC
Number of
56 k ; R
100 pF; R
13
10
16
TC
n
8
and C
8
n 1
S
).
S
120k
counts the output
2 R
TC
Count
65536
8192
1024
256
2
n