M41ST85YMH6E STMicroelectronics, M41ST85YMH6E Datasheet

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FEATURES SUMMARY 5.0 OR 3.0V OPERATING VOLTAGE SERIAL INTERFACE SUPPORTS I (400 KHz) NVRAM SUPERVISOR FOR EXTERNAL LPSRAM OPTIMIZED FOR MINIMAL INTERCONNECT TO MCU 2.5 TO 5.5V OSCILLATOR OPERATING VOLTAGE AUTOMATIC SWITCH-OVER AND DESELECT CIRCUITRY CHOICE OF POWER-FAIL DESELECT VOLTAGES ...

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M41ST85Y, M41ST85W TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Power-fail INPUT/OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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M41ST85Y, M41ST85W SUMMARY DESCRIPTION The M41ST85Y/W Serial TIMEKEEPER troller SRAM is a low power 512-bit, static CMOS SRAM organized as 64 words by 8 bits. A built-in 32.768 kHz oscillator (external crystal controlled) and 8 bytes of the SRAM (see ...

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Figure 3. Logic Diagram V BAT ( SCL SDA EX M41ST85Y M41ST85W RSTIN1 RSTIN2 WDI PFI V SS Note: 1. For 28-pin, 300mil embedded crystal SOIC only. Figure 4. 28-pin SOIC Connections SQW ...

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M41ST85Y, M41ST85W Figure 6. Block Diagram SDA INTERFACE SCL (2) 32KHz Crystal OSCILLATOR WDI BAT RSTIN1 RSTIN2 EX PFI 1.25V (Internal) Note: 1. Open drain output 2. Integrated into SOIC package for MX package option. 6/34 REAL ...

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Figure 7. Hardware Hookup Regulator Unregulated V IN Voltage Pushbutton R1 R2 Note: 1. Required for embedded crystal (MX) package only. M41ST85Y SCL WDI RSTIN1 RSTIN2 Reset PFI (1) IRQ/FT/OUT V BAT V SS M41ST85Y, ...

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M41ST85Y, M41ST85W OPERATING MODES The M41ST85Y/W clock operates as a slave de- vice on the serial bus. Access is obtained by im- plementing a start condition followed by the correct slave address (D0h). The 64 bytes con- tained in the ...

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Figure 8. Serial Bus Data Transfer Sequence CLOCK DATA START CONDITION Figure 9. Acknowledgement Sequence START SCL FROM MASTER DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER Figure 10. WRITE Cycle Timing: RTC & External SRAM Control Signals EX E ...

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M41ST85Y, M41ST85W READ Mode In this mode the master reads the M41ST85Y/W slave after setting the slave address (see 11., page 10). Following the WRITE Mode Control Bit (R/W=0) and the Acknowledge Bit, the word address 'An' is written to ...

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Figure 13. Alternate READ Mode Sequence BUS ACTIVITY: MASTER SDA LINE S BUS ACTIVITY: SLAVE ADDRESS WRITE Mode In this mode the master transmitter transmits to the M41ST85Y/W slave receiver. Bus protocol is shown in Figure 14., page START condition ...

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M41ST85Y, M41ST85W Data Retention Mode With valid V applied, the M41ST85Y/W can be CC accessed as described above with READ or WRITE Cycles. Should the supply voltage decay, the M41ST85Y/W will automatically deselect, write protecting itself (and any external SRAM) ...

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CLOCK OPERATION The eight byte clock register (see 2., page 14) is used to both set the clock and to read the date and time from the clock binary coded decimal format. Tenths/Hundredths of Sec- onds, Seconds, Minutes, ...

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M41ST85Y, M41ST85W ® Table 2. TIMEKEEPER Register Map Address D7 D6 00h 0.1 Seconds 01h ST 10 Seconds 02h 0 10 Minutes 03h CEB CB 04h TR 0 05h 0 0 06h 0 0 07h 10 Years 08h OUT FT ...

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Calibrating the Clock The M41ST85Y/W is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not exceed +/–35 ppm (parts per million) oscillator frequency error which equates to ...

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M41ST85Y, M41ST85W Figure 15. Crystal Accuracy Across Temperature Frequency (ppm –20 –40 –60 –80 –100 –120 –140 –160 –40 –30 –20 Figure 16. Calibration Waveform NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION 16/ – T ...

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Setting Alarm Clock Registers Address locations 0Ah-0Eh contain the alarm set- tings. The alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, ...

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M41ST85Y, M41ST85W Figure 18. Back-Up Mode Alarm Waveform PFD V SO ABE, AFE Bits in Interrupt Register AF bit in Flags Register IRQ/FT/OUT Watchdog Timer The watchdog timer can be used to detect an out- of-control microprocessor. ...

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Square Wave Output The M41ST85Y/W offers the user a programma- ble square wave function which is output on the SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These fre- quencies are listed in Table 4. ...

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M41ST85Y, M41ST85W Power-on Reset The M41ST85Y/W continuously monitors V When V falls to the power fail detect trip point, CC the RST pulls low (open drain) and remains low on power-up for t after V rec CC The RST pin ...

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Power-fail INPUT/OUTPUT The Power-Fail Input (PFI) is compared to an in- ternal reference voltage (1.25V). If PFI is less than the power-fail threshold (V PFI Output (PFO) will go low. This function is intended for use as an undervoltage detector ...

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M41ST85Y, M41ST85W t Bit rec Bit D7 of Clock Register 04h contains the t (TR). t refers to the automatic continuation of rec the deselect time after V reaches V CC lows for a voltage settling time before WRITEs may ...

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... CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets. not implied. Exposure to Absolute Maximum Rat- ing conditions for extended periods may affect de- vice reliability. STMicroelectronics SURE Program and other rel- evant quality documents. Parameter SNAPHAT Off, Oscillator Off) CC ...

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M41ST85Y, M41ST85W DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests ...

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Table 11. DC Characteristics Sym Parameter Battery Current OSC ON (2) I BAT Battery Current OSC OFF I Supply Current CC1 Supply Current I CC2 (Standby) Input Leakage Current ( Input Leakage Current (PFI) Output Leakage (4) I ...

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M41ST85Y, M41ST85W Figure 21. Bus Timing Requirements Sequence SDA tBUF SCL P S Table 12. AC Characteristics Symbol f SCL Clock Frequency SCL t Time the bus must be free before a new transmission can start BUF ...

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Figure 22. Power Down/Up Mode AC Waveforms PFD (max) V PFD (min tPD PFO INPUTS RECOGNIZED RST OUTPUTS VALID (PER CONTROL INPUT) E CON Table 13. Power Down/Up AC Characteristics Symbol (2) V (max) ...

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M41ST85Y, M41ST85W PACKAGE MECHANICAL INFORMATION Figure 23. SOH28 – 28-lead Plastic Small Outline, Battery SNAPHAT, Package Outline SOH-A Note: Drawing is not to scale. Table 14. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package ...

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Figure 24. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline Note: Drawing is not to scale. Table 15. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Mechanical Data Symbol Typ ...

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M41ST85Y, M41ST85W Figure 25. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline Note: Drawing is not to scale. Table 16. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Mechanical Data Symbol Typ A A1 ...

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Figure 26. SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Outline SO-E Note: Drawing is not to scale. Table 17. SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Mech. Data Symbol ...

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M41ST85Y, M41ST85W PART NUMBERING Table 18. Ordering Information Scheme Example: Device Type M41ST Supply Voltage and Write Protect Voltage 85Y = V = 4.5 to 5.5V; 4.20V CC 85W = V = 2.7 to 3.6V; 2.55V CC Package (1) MH ...

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REVISION HISTORY Table 20. Document Revision History Date Rev. # August 2000 1.0 First issue 24-Aug-00 1.1 Block Diagram added (Figure 3) t Table removed, cross references corrected 12-Oct-00 1.2 rec 18-Dec-00 2.0 Reformatted, TOC added, and PFI Input Leakage ...

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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...