MT49H32M18HT-33:A Micron Technology Inc, MT49H32M18HT-33:A Datasheet
MT49H32M18HT-33:A
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MT49H32M18HT-33:A Summary of contents
Page 1
... Vext, 1.8V Vdd, 1.5V or 1.8V Vddq I/O • On-die termination (ODT) Rtt PDF: 09005aef80fe62fb/Source: 09005aef809f284b 576Mb_RLDRAM_II_CIO_D1.fm - Rev. H 6/09 EN Products and specifications discussed herein are subject to change by Micron without notice. 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II ® II Options • Clock cycle timing – ...
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... Due to space limitations, BGA-packaged components have an abbreviated part marking that is different from the part number. Micron’s BGA Part Marking Decoder is available on Micron’s Web site at micron.com. PDF: 09005aef80fe62fb/Source: 09005aef809f284b 576Mb_RLDRAM_II_CIO_D1.fm - Rev. H 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II - I/O Package Configuration ...
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... TAP Registers .70 TAP Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 PDF: 09005aef80fe62fb/Source: 09005aef809f284b 576Mb_RLDRAM_CIOTOC.fm - Rev. H 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II 3 Table of Contents Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. ...
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... List of Figures Figure 1: 576Mb RLDRAM II CIO Part Numbers Figure 2: Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Figure 3: 64 Meg x 9 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Figure 4: 32 Meg x 18 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Figure 5: 16 Meg x 36 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Figure 6: 144-Ball µBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Figure 7: 144-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Figure 8: Clock Input .21 Figure 9: Nominal tAS/tCS/tDS and tAH/tCH/tDH Slew Rate ...
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... Table 30: Boundary Scan (Exit) Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 PDF: 09005aef80fe62fb/Source: 09005aef809f284b 576Mb_RLDRAM_CIOLOT.fm - Rev. H 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II 5 Lisf of Tables Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. ...
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... Read and write accesses to the RLDRAM are burst-oriented. The burst length (BL) is programmable from setting the mode register. The device is supplied with 2.5V and 1.8V for the core and 1.5V or 1.8V for the output drivers ...
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... State Diagram Figure 2: Simplified State Diagram WRITE PDF: 09005aef80fe62fb/Source: 09005aef809f284b 576Mb_RLDRAM_II_CIO_D2.fm - Rev. H 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II Initialization sequence DSEL/NOP MRS Automatic sequence Command sequence 7 State Diagram READ AREF Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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Functional Block Diagrams Figure 3: 64 Meg x 9 Functional Block Diagram ZQ ODT control CK CK# Control CS# logic REF# WE# Refresh 14 counter Mode register Row- address MUX A0–A21 Address 25 BA0–BA2 register 3 1 ...
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Figure 4: 32 Meg x 18 Functional Block Diagram ZQ ODT control CK CK# Control CS# logic REF# WE# Refresh 14 counter Mode register Row- address MUX A0–A20 Address 24 BA0–BA2 register Notes: ...
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Figure 5: 16 Meg x 36 Functional Block Diagram ZQ ODT control CK CK# Control CS# logic REF# WE# Refresh 14 counter Mode register Row- address MUX A0–A19 Address 24 BA0–BA2 register Notes: ...
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... Do not use. This signal is internally connected and has parasitic characteristics of an I/O. This may optionally be connected to GND. Note that if ODT is enabled, these pins will be con- nected to Vtt. PDF: 09005aef80fe62fb/Source: 09005aef809f284b 576Mb_RLDRAM_II_CIO_D2.fm - Rev. H 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM Vss ...
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... Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This may optionally be connected to GND. Note that if ODT is enabled, these pins will be con- nected to Vtt. PDF: 09005aef80fe62fb/Source: 09005aef809f284b 576Mb_RLDRAM_II_CIO_D2.fm - Rev. H 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM Vss ...
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... Reserved for future use. This may optionally be connected to GND. 2. Reserved for future use. This signal is internally connected and has parasitic characteristics of an address input signal. This may optionally be connected to GND. PDF: 09005aef80fe62fb/Source: 09005aef809f284b 576Mb_RLDRAM_II_CIO_D2.fm - Rev. H 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM Vss ...
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... Output data clocks: QKx and QKx# are opposite polarity, output data clocks. They are free- running, and during READs, are edge-aligned with data output from the RLDRAM. QKx# is ideally 180 degrees out of phase with QKx. For the x36 device, QK0 and QK0# are aligned with DQ0– ...
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... Ag, 0.5% Cu). Dimensions apply solder balls post-reflow on Ø0.39 SMD ball pads. 17 CTR 1 TYP Notes: 1. All dimensions are in millimeters. PDF: 09005aef80fe62fb/Source: 09005aef809f284b 576Mb_RLDRAM_II_CIO_D2.fm - Rev. H 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II 10.6 CTR 10º TYP 0.73 ±0.1 Ball ...
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... Ball A12 17.00 8.50 4.40 11.00 ±0.10 Notes: 1. All dimensions are in millimeters. PDF: 09005aef80fe62fb/Source: 09005aef809f284b 576Mb_RLDRAM_II_CIO_D2.fm - Rev. H 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II 0.75 ±0.05 8.80 Ball A1 Ball A1 ID 9.25 ±0. 18.50 ±0.10 1.00 TYP C L 5.50 ± ...
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... Continuous example data; Measurement is taken during continuous READ PDF: 09005aef80fe62fb/Source: 09005aef809f284b 576Mb_RLDRAM_II_CIO_D2.fm - Rev. H 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II Condition Isb1 (Vdd) x9/x18 Isb1 (Vdd) x36 Isb2 (Vdd) x9/x18 Isb2 (Vdd) x36 ...
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... AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 2 V/ns in the range between Vil(AC) and Vih(AC). PDF: 09005aef80fe62fb/Source: 09005aef809f284b 576Mb_RLDRAM_II_CIO_D2.fm - Rev. H 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM MIN MIN. ...
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... DC value. Thus, from Vddq/2, Vref is allowed ±2% Vddq/2 for DC error and an addi- tional ±2% Vddq/2 for AC noise. This measurement taken at the nearest Vref bypass capacitor. PDF: 09005aef80fe62fb/Source: 09005aef809f284b 576Mb_RLDRAM_II_CIO_D2.fm - Rev. H 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II Conditions Symbol – Vext – ...
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... IOL flows into the device. 10. If MRS bit use RQ = 250Ω in the equation in lieu of presence of an external imped- ance matched resistor. 11. For Vol and Voh, refer to the RLDRAM II HSPICE or IBIS driver models. Table 8: Input AC Logic Levels Notes 1–3 apply to entire table; Unless otherwise noted: +0°C ≤ T ...
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... CK and CK# must meet at least Vid(DC) MIN when static and centered around Vddq/2. 3. Minimum peak-to-peak swing violation to tristate CK and CK# after the part is initialized. PDF: 09005aef80fe62fb/Source: 09005aef809f284b 576Mb_RLDRAM_II_CIO_D2.fm - Rev. H 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II Symbol Vin(DC) V (DC) ...
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... The above descriptions also pertain to data setup and hold derating when CK/CK# are replaced with DK/DK#. PDF: 09005aef80fe62fb/Source: 09005aef809f284b 576Mb_RLDRAM_II_CIO_D2.fm - Rev. H 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM specifications when the slew rate of any of these input signals is less than t ...
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... PDF: 09005aef80fe62fb/Source: 09005aef809f284b 576Mb_RLDRAM_II_CIO_D2.fm - Rev. H 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM AS/ CS Vih(AC MIN to CK/CK# AH/ Crossing Crossing to Vref CK, CK# Differential Slew Rate: 2.0 V/ns –100 –100 – ...
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... PDF: 09005aef80fe62fb/Source: 09005aef809f284b 576Mb_RLDRAM_II_CIO_D2.fm - Rev. H 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM Vih(AC) MIN t to CK/CK# DH CK/CK# Crossing Crossing to Vref DK, DK# Differential Slew Rate: 2.0 V/ns –100 –100 – ...
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... Input/output capacitance (DQ, DM, and QK/QK#) Clock capacitance (CK/CK#, and DK/DK#) JTAG pins Notes: 1. Capacitance is not tested on ZQ pin. 2. JTAG pins are tested at 50 MHz. PDF: 09005aef80fe62fb/Source: 09005aef809f284b 576Mb_RLDRAM_II_CIO_D2.fm - Rev. H 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM and AH/ CH/ ...
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... QK edge to output t QKQ1 data edge t QK edge to any QKQ output data edge t QK edge to QVLD QKVLD PDF: 09005aef80fe62fb/Source: 09005aef809f284b 576Mb_RLDRAM_II_CIO_D2.fm - Rev. H 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II -18 -25E Min Max Min Max 1.875 2.7 2.5 5 ...
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... Notes 1–4 (page 28) apply to the entire table Description Symbol t DVW Data valid window Refresh t Average periodic REFI refresh interval PDF: 09005aef80fe62fb/Source: 09005aef809f284b 576Mb_RLDRAM_II_CIO_D2.fm - Rev. H 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II -18 -25E Min Max Min Max t t QHP - – QHP - – ...
Page 28
... QKQ takes into account the skew between any QKx and any improve efficiency, eight AREF commands (one for each bank) can be posted to the RLDRAM on consecutive cycles at periodic intervals of 1.95µs. PDF: 09005aef80fe62fb/Source: 09005aef809f284b 576Mb_RLDRAM_II_CIO_D2.fm - Rev. H 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM 50Ω Test point ...
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... Table 15. For designs that are expected to last several years and require the flexi- bility to use several DRAM die shrinks, consider using final target theta values (rather than existing values) to account for increased thermal impedances from the die size reduction. The RLDRAM device’ ...
Page 30
... Figure 10: Example Temperature Test Point Location Test point PDF: 09005aef80fe62fb/Source: 09005aef809f284b 576Mb_RLDRAM_II_CIO_D2.fm - Rev. H 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II 18.50 9.25 5.50 11.00 30 Temperature and Thermal Impedance Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 31
... Description of Commands Command DSEL/NOP The NOP command is used to perform a no operation to the RLDRAM, which essentially deselects the chip. Use the NOP command to prevent unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Output values depend on command history. ...
Page 32
... During an MRS command, the address inputs A0–A17 are sampled and stored in the mode register. After issuing a valid MRS command, command can be issued to the RLDRAM. This statement does not apply to the consecu- tive MRS commands needed for internal logic reset during the initialization routine. The MRS command can only be issued when all banks are idle and no bursts are in progress ...
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... A10–A17 must be set to zero; A18–An = “Don’t Care.” not used in MRS not available. 4. DLL RESET turns the DLL off. 5. Available in 576Mb part only. 6. ±30% temperature variation. PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II A17 A10 17–10 ...
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... Burst Length (BL) Burst length is defined by M3 and M4 of the mode register. Read and write accesses to the RLDRAM are burst-oriented, with the burst length being programmable Figure 12 on page 35 illustrates the different burst lengths with respect to a READ command. Changes in the burst length affect the width of the address bus (see Table 20 on page 35 for details) ...
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... DRAM. In multiplexed address mode, the address can be provided to the RLDRAM in two parts that are latched into the memory with two consecutive rising clock edges. This provides the advantage of only ...
Page 36
... The data bus efficiency in continuous burst mode is only affected when using the setting since the device requires two clocks to read and write the data. The bank addresses are delivered to the RLDRAM at the same time as the WRITE and READ command and the first address part, Ax. Table 22 on page 61 and Table 23 on page 62 show the addresses needed for both the first and second rising clock edges (Ax and Ay, respectively) ...
Page 37
... READ command is issued. Similarly, ODT is designed to switch on at the DQs after the RLDRAM has issued the last piece of data. The DM pin will always be terminated. See section entitled "Operations" on page 41 for relevant timing diagrams. Table 21: On-Die Termination DC Parameters Description Termination voltage ...
Page 38
... WRITE command. During WRITE commands, data will be registered at both edges of DK according to the programmed burst length (BL). The RLDRAM operates with a WRITE latency (WL) that is one cycle longer than the programmed READ latency (RL + 1), with the first valid data registered at the first rising DK edge WL cycles after the WRITE command ...
Page 39
... BANK ADDRESS PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II t QKQ0 is referenced to DQ0–DQ17 for the x36 configuration and DQ0–DQ8 t QKQ1 is the skew between QK1 and the last valid data edge ...
Page 40
... RLDRAM requires 128K cycles at an average periodic interval of 0.24µs MAX (actual periodic refresh interval is 32ms/16K rows/8 = 0.244µs). To improve efficiency, eight AREF commands (one for each bank) can be posted to the RLDRAM at periodic intervals of 1.95µs (32ms/16K rows = 1.95µs). Figure 31 on page 55 illustrates an example of a refresh sequence ...
Page 41
... Vtt) and start clock as soon as the supply voltages Vref and Vtt. Although there is no timing relation between Vext t MRSC does not need to be met between these consecutive (DC) on CK/CK# can not be met prior to being applied to the RLDRAM, placing Apply Vddq before (DC) prior to being applied ...
Page 42
... The sequence of the eight AUTO REFRESH commands (with respect to the 1,024 NOP com- mands) does not matter required for any operation, AUTO REFRESH command and a subsequent VALID command to the same bank. PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM ...
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... The sequence of the eight AUTO REFRESH commands (with respect to the 1,024 NOP com- mands) does not matter required for any operation, AUTO REFRESH command and a subsequent VALID command to the same bank. PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II V and V ramp DD, ...
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... CKDK (MAX) DK Notes data-in for bank a and address n; subsequent elements of burst are applied follow- ing DI an PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM NOP NOP t CKDK t CKDK 44 T6 T6n T4 T5 T5n NOP ...
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... Each WRITE command may be to any bank; if the second WRITE is to the same bank must be met. 5. Nominal conditions are assumed for specifications not defined. PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM WRITE NOP WRITE ...
Page 46
... data-out from bank b and address n. 3. Two subsequent elements of each burst follow DI an and DO bn Nominal conditions are assumed for specifications not defined. PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM READ NOP Bank b, ...
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... Only one NOP separating the WRITE and READ would have led to contention on the data bus because of the input and output data timing conditions being used. 6. Nominal conditions are assumed for specifications not defined. PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM NOP ...
Page 48
... Notes data-in for bank a and address n. 2. Subsequent elements of burst are provided on following clock edges Nominal conditions are assumed for specifications not defined. PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM NOP NOP ...
Page 49
... Notes data-out from bank a and address an. 2. Three subsequent elements of the burst are applied following DO an Nominal conditions are assumed for specifications not defined. PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM NOP ...
Page 50
... Bank address can be to any bank, but the subsequent READ can only be to the same bank has been met. 6. Data from the READ commands to banks c and d will appear on subsequent clock cycles that are not shown. PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM READ READ READ ...
Page 51
... data-in for bank b and address n. 3. Three subsequent elements of each burst follow DI bn and each DO an Nominal conditions are assumed for specifications not defined. PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM WRITE NOP ...
Page 52
... QKQ0 is referenced to DQ0–DQ8. 3. Minimum data valid window ( t QHP - ( PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II t QHP 1 t QHP 1 t QKQ0 (MAX QKQ0 (MAX QKQ0 (MIN QKQ0 (MIN DVW 3 t DVW 3 ...
Page 53
... QKQ1 is referenced to DQ9–DQ17 QKQ takes into account the skew between any QKx and any DQ. PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II t QHP 1 t QHP 1 t QKQ0 (MAX QKQ0 (MAX QKQ0 (MAX) 2 ...
Page 54
... QKQ1 is referenced to DQ18–DQ35 QKQ takes into account the skew between any QKx and any DQ. PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II t QHP 1 t QHP 1 t QKQ0 (MAX QKQ0 (MAX QKQ0 (MIN) 2 ...
Page 55
... Notes: 1. AREFx = AUTO REFRESH command to bank x. 2. ACx = any command to bank x; ACy = any command to bank y. 3. BAx = bank address to bank x; BAy = bank address to bank y. PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM CK# ...
Page 56
... DQ ODT Notes data out from bank a and address followed by the remaining bits of the burst. 3. Nominal conditions are assumed for specifications not defined. PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM NOP NOP NOP ...
Page 57
... data-out from bank a and address data-in for bank b and address One subsequent element of each burst appears after each DO an and DI bn. 4. Nominal conditions are assumed for specifications not defined. PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM READ NOP ...
Page 58
... WE# REF# ADDRESS Ax Ay BANK BA ADDRESS Notes: 1. The minimum setup and hold times of the two address parts are defined PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II WRITE MRS Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
Page 59
... Address A5 must be set HIGH. This and the following step set the desired mode register once the RLDRAM is in multiplexed address mode. 5. Any command or address. 6. The above sequence must be followed in order to power up the RLDRAM in the multiplexed address mode. 7. DLL must be reset and CK# must separated at all times to prevent bogus commands from being issued. ...
Page 60
... BA0–BA2 are “Don’t Care.” 8. Addresses A0, A3, A4, A5, A8, and A9 must be set as shown in order to activate the mode register in the multiplexed address mode. PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II Ax A18 . . . A10 ...
Page 61
... Address Mapping in Multiplexed Address Mode Table 22: 576Mb Address Mapping in Multiplexed Address Mode Data Burst Width Length Ball A0 x36 x18 A20 A20 A20 Notes “Don’t Care.” PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II Address A21 ...
Page 62
... Configuration Tables in Multiplexed Address Mode In multiplexed address mode, the read and write latencies are increased by one clock cycle. However, the RLDRAM cycle time remains the same as when in non-multiplexed address mode. Table 23: Cycle Time and READ/WRITE Latency Configuration Table in Multiplexed Mode Notes 1–2 apply to the entire table ...
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... Three subsequent elements of the burst are applied following DI for each bank. 4. Each WRITE command may be to any bank; if the second WRITE is to the same bank, must be met. PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM WRITE ...
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... Nominal conditions are assumed for specifications not defined. 6. Bank address can be to any bank, but the subsequent READ can only be to the same bank has been met. PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM READ NOP Ax ...
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... Bank address can be to any bank, but the subsequent READ can only be to the same bank has been met. 7. Data from the READ commands to banks b through bank d will appear on subsequent clock cycles that are not shown. PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM NOP READ NOP ...
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... Three subsequent elements of the burst which appear following DI bn are not all shown. 7. Bank address can be to any bank, but the WRITE command can only be to the same bank has been met. PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM WRITE NOP ...
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... M8 needs to be set to 0 until the JTAG testing of the pin is complete. Note that upon power up, the default state of MRS bit M8 is low. If the RLDRAM boundary scan register used upon power up and prior to the initialization of the RLDRAM device imperative that the CK and CK# pins meet V (DC) or CS# be held HIGH from power up until testing ...
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... PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II IEEE 1149.1 Serial Boundary Scan (JTAG) 68 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Figure 44: TAP Controller Block Diagram TDI TCK TMS Notes 112 for all configurations. PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II IEEE 1149.1 Serial Boundary Scan (JTAG) reset Select Run-test/ Idle DR-scan 0 ...
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... Table 30 on page 75 shows the order in which the bits are connected. Each bit corre- sponds to one of the balls on the RLDRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the capture-DR state when the IDCODE command is loaded in the instruction register ...
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... The user must be aware that the TAP controller clock can only operate at a frequency MHz, while the RLDRAM clock operates significantly faster. Because there is a large difference between the clock frequencies possible that during the capture-DR state, an input or output will undergo a transition ...
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... TCK TMS TDI TAP Select-DR- Exit 2-IR Update-IR CONTROLLER STATE TDO PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II IEEE 1149.1 Serial Boundary Scan (JTAG Select-DR- Select-IR- Capture-IR SCAN SCAN T12 T13 T14 ...
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... Capture setup Hold times TMS hold Capture hold t Notes and ary scan register. PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II IEEE 1149.1 Serial Boundary Scan (JTAG (TCK) t THTL t TLTH t MVTH t THMX (TMS) ...
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... Scan Register Sizes Register Name Instruction Bypass ID Boundary scan PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II IEEE 1149.1 Serial Boundary Scan (JTAG) Condition Symbol Vih Vil 0V ≤ Vin ≤ Vdd ILI Output disabled, ILO 0V ≤ ...
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... U11 PDF: 09005aef80a41b46/Source: 09005aef809f284b RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN 576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II IEEE 1149.1 Serial Boundary Scan (JTAG) Captures I/O ring contents; Places the boundary scan register between TDI and TDO; This operation does not affect RLDRAM operations Loads the ID register with the vendor ID code and places the register between TDI and TDO ...
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... S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. RLDRAM is a trademark of Qimonda AG in various countries, and is used by Micron Technology, inc. under license from Qimonda. All other trademarks are the property of their respective owners. ...