MT49H32M18HT-33:A Micron Technology Inc, MT49H32M18HT-33:A Datasheet - Page 67

• Manufacturer Part Number: MT49H32M18HT-33:A
• Manufacturer: Micron Technology Inc
• Type: RLDRAMr

Specifications of MT49H32M18HT-33:A

• Organization: 32Mx18
• Address Bus: 24b
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 609mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

IEEE 1149.1 Serial Boundary Scan (JTAG)
Disabling the JTAG Feature
Test Access Port (TAP)
Test Clock (TCK)
Test Mode Select (TMS)
PDF: 09005aef80a41b46/Source: 09005aef809f284b
RLDRAM_II_CIO_Core.fm - Rev. D 6/09 EN
RLDRAM incorporates a serial boundary-scan test access port (TAP) for the purpose of
testing the connectivity of the device once it has been mounted on a printed circuit
board (PCB). As the complexity of PCB high-density surface mounting techniques
increases, the boundary-scan architecture is a valuable resource for interconnectivity
debug. This port operates in accordance with IEEE Standard 1149.1-2001 (JTAG) with
the exception of the ZQ pin. To ensure proper boundary-scan testing of the ZQ pin, MRS
bit M8 needs to be set to 0 until the JTAG testing of the pin is complete. Note that upon
power up, the default state of MRS bit M8 is low.
If the RLDRAM boundary scan register is to be used upon power up and prior to the
initialization of the RLDRAM device, it is imperative that the CK and CK# pins meet
V
inadvertent MRS commands to be loaded, and subsequently cause unexpected results
from address pins that are dependent upon the state of the mode register. If these
measures cannot be taken, the part must be initialized prior to boundary scan testing. If
a full initialization is not practical or feasible prior to boundary scan testing, a single
MRS command with desired settings may be issued instead. After the single MRS
command is issued, the
testing.
The input signals of the test access port (TDI, TMS, and TCK) use Vdd as a supply, while
the output signal of the TAP (TDO) uses Vddq.
The JTAG test access port utilizes the TAP controller on the RLDRAM, from which the
instruction register, boundary scan register, bypass register, and ID register can be
selected. Each of these functions of the TAP controller is described in detail below.
It is possible to operate RLDRAM without using the JTAG feature. To disable the TAP
controller, TCK must be tied LOW (Vss) to prevent clocking of the device. TDI and TMS
are internally pulled up and may be unconnected. They may alternately be connected to
Vdd through a pull-up resistor. TDO should be left unconnected. Upon power-up, the
device will come up in a reset state, which will not interfere with the operation of the
device.
The test clock is used only with the TAP controller. All inputs are captured on the rising
edge of TCK. All outputs are driven from the falling edge of TCK.
The TMS input is used to give commands to the TAP controller and is sampled on the
rising edge of TCK.
All of the states in Figure 43: “TAP Controller State Diagram,” on page 69 are entered
through the serial input of the TMS pin. A “0” in the diagram represents a LOW on the
TMS pin during the rising edge of TCK while a “1” represents a HIGH on TMS.
ID
(DC) or CS# be held HIGH from power up until testing. Not doing so could result in
576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II
t
MRSC parameter must be satisfied prior to boundary scan
67
IEEE 1149.1 Serial Boundary Scan (JTAG)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.