MT49H32M18HT-33:A Micron Technology Inc, MT49H32M18HT-33:A Datasheet - Page 18

• Manufacturer Part Number: MT49H32M18HT-33:A
• Manufacturer: Micron Technology Inc
• Type: RLDRAMr

Specifications of MT49H32M18HT-33:A

• Organization: 32Mx18
• Address Bus: 24b
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 609mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

PDF: 09005aef80fe62fb/Source: 09005aef809f284b
576Mb_RLDRAM_II_CIO_D2.fm - Rev. H 6/09 EN
Notes:
1. Idd specifications are tested after the device is properly initialized. +0°C ≤ T
2.
3. Input slew rate is specified in Table 8 on page 20.
4. Definitions for Idd conditions:
5. CS# is HIGH unless a READ, WRITE, AREF, or MRS command is registered. CS# never transi-
6. Idd parameters are specified with ODT disabled.
7. Tests for AC timing, Idd, and electrical AC and DC characteristics may be conducted at nom-
8. Idd tests may use a Vil-to-Vih swing of up to 1.5V in the test environment, but input timing
4b. HIGH is defined as Vin ≥ Vih(AC) MIN.
4d. Floating is defined as inputs at Vref = Vddq/2.
4g. Sequential bank access is defined as the bank address incrementing by one every
4h. Cyclic bank access is defined as the bank address incrementing by one for each com-
4a. LOW is defined as Vin ≤ Vil(AC) MAX.
4e. Continuous data is defined as half the DQ signals changing between HIGH and LOW
4c. Stable is defined as inputs remaining at a HIGH or LOW level.
4f. Continuous address is defined as half the address signals changing between HIGH and
≤ Vdd ≤ +1.9V, +2.38V ≤ Vext ≤ +2.63V, +1.4V ≤ Vddq ≤ Vdd, Vref = Vddq/2.
t
tions more than once per clock cycle.
inal reference/supply voltage levels, but the related specifications and device operations are
tested for the full voltage range specified.
is still referenced to Vref (or to the crossing point for CK/CK#), and parameter specifications
are tested for the specified AC input levels under normal use conditions. The minimum slew
rate for the input signals used to test the device is 2 V/ns in the range between Vil(AC) and
Vih(AC).
CK =
every half clock cycle (twice per clock).
LOW every clock cycle (once per clock).
mand access. For BL = 2 this is every clock, for BL = 4 this is every other clock, and for
BL = 8 this is every fourth clock.
576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II
t
DK = MIN,
t
RC = MIN.
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Electrical Specifications – Idd
©2004 Micron Technology, Inc. All rights reserved.
C
≤ +95°C; +1.7V
t
RC.