MT49H32M18HT-33:A Micron Technology Inc, MT49H32M18HT-33:A Datasheet - Page 14

• Manufacturer Part Number: MT49H32M18HT-33:A
• Manufacturer: Micron Technology Inc
• Type: RLDRAMr

Specifications of MT49H32M18HT-33:A

• Organization: 32Mx18
• Address Bus: 24b
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 609mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Table 4:
PDF: 09005aef80fe62fb/Source: 09005aef809f284b
576Mb_RLDRAM_II_CIO_D2.fm - Rev. H 6/09 EN
DQ0–DQ35
QKx, QKx#
WE#, REF#
BA0–BA2
TMS, TDI
Symbol
DK, DK#
A0–A21
CK, CK#
QVLD
Vddq
DNU
TDO
Vext
Vssq
Vref
Vdd
TCK
A22
CS#
DM
Vss
Vtt
ZQ
NF
Ball Descriptions
Output
Output
Output
Supply
Supply
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
–
–
–
Address inputs: A0–A21 define the row and column addresses for READ and WRITE operations.
During a MODE REGISTER SET, the address inputs define the register settings. They are sampled
at the rising edge of CK.
Bank address inputs: Select to which internal bank a command is being applied.
Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on
the rising edge of CK. CK# is ideally 180 degrees out of phase with CK.
Chip select: CS# enables the command decoder when LOW and disables it when HIGH. When
the command decoder is disabled, new commands are ignored, but internal operations continue.
Data input: The DQ signals form the 36-bit data bus. During READ commands, the data is
referenced to both edges of QKx. During WRITE commands, the data is sampled at both edges of
DK.
Input data clock: DK and DK# are the differential input data clocks. All input data is referenced
to both edges of DK. DK# is ideally 180 degrees out of phase with DK. For the x36 device, DQ0–
DQ17 are referenced to DK0 and DK0# and DQ18–DQ35 are referenced to DK1 and DK1#. For the
x9 and x18 devices, all DQs are referenced to DK and DK#. All DKx and DKx# pins must always be
supplied to the device.
Input data mask: The DM signal is the input mask signal for WRITE data. Input data is masked
when DM is sampled HIGH. DM is sampled on both edges of DK (DK1 for the x36 configuration).
Tie signal to ground if not used.
IEEE 1149.1 clock input: This ball must be tied to Vss if the JTAG function is not used.
IEEE 1149.1 test inputs: These balls may be left as no connects if the JTAG function is not used.
Command inputs: Sampled at the positive edge of CK, WE# and REF# define (together with
CS#) the command to be executed.
Input reference voltage: Nominally Vddq/2. Provides a reference voltage for the input buffers.
External impedance (25–60Ω): This signal is used to tune the device outputs to the system data
bus impedance. DQ output impedance is set to 0.2 × RQ, where RQ is a resistor from this signal to
ground. Connecting ZQ to GND invokes the minimum impedance mode. Connecting ZQ to Vdd
invokes the maximum impedance mode. Refer to Figure 11 on page 33 to activate this function.
Output data clocks: QKx and QKx# are opposite polarity, output data clocks. They are free-
running, and during READs, are edge-aligned with data output from the RLDRAM. QKx# is
ideally 180 degrees out of phase with QKx. For the x36 device, QK0 and QK0# are aligned with
DQ0–DQ17, and QK1 and QK1# are aligned with DQ18–DQ35. For the x18 device, QK0 and QK0#
are aligned with DQ0–DQ8, while QK1 and QK1# are aligned with Q9–Q17. For the x9 device, all
DQs are aligned with QK0 and QK0#.
Data valid: The QVLD pin indicates valid output data. QVLD is edge-aligned with QKx and QKx#.
IEEE 1149.1 test output: JTAG output. This ball may be left as no connect if the JTAG function
is not used.
Power supply: Nominally, 1.8V. See Table 7 on page 19 for range.
DQ power supply: Nominally, 1.5V or 1.8V. Isolated on the device for improved noise immunity.
See Table 7 on page 19 for range.
Power supply: Nominally, 2.5V. See Table 7 on page 19 for range.
Ground.
DQ ground: Isolated on the device for improved noise immunity.
Power supply: Isolated termination supply. Nominally, Vddq/2. See Table 7 on page 19 for
range.
Reserved for future use: This signal is not connected and may be connected to ground.
Do not use: These balls may be connected to ground. Note that if ODT is enabled, these pins will
be connected to Vtt.
No function: These balls can be connected to ground.
576Mb: x9, x18, x36 2.5V Vext, 1.8V Vdd, HSTL, CIO, RLDRAM II
14
Description
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Ball Assignments and Descriptions
©2004 Micron Technology, Inc. All rights reserved.