PEF80912HV1.4XT Infineon Technologies, PEF80912HV1.4XT Datasheet - Page 65
PEF80912HV1.4XT
Manufacturer Part Number
PEF80912HV1.4XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF80912HV1.4XT.pdf
(85 pages)
Specifications of PEF80912HV1.4XT
Lead Free Status / Rohs Status
Compliant
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4
4.1
•
Parameter
Ambient temperature under bias
Storage temperature
Maximum Voltage on V
Maximum Voltage on any pin with respect to
ground
ESD integrity (according EIA/JESD22-A114B (HBM)): 2 kV
Note: Stress above those listed here may cause permanent damage to the device.
Line Overload Protection
The Q-SMINT
(CDM), EIA/JESD22-A114B (HBM) and to Latch-up tests according to JEDEC EIA /
JESD78. From these tests the following max. input currents are derived
•
Table 17
Test
ESD
Latch-up
DC
Data Sheet
Exposure to absolute maximum ratings conditions for extended periods may affect
device reliability.
Electrical Characteristics
Absolute Maximum Ratings
Maximum Input Currents
O is compliant to ESD tests according to ANSI / EOS / ESD-S 5.1-1993
DD
Pulse Width
100 ns
5 ms
--
Current
1.3 A
+/-200 mA
10 mA
57
Symbol Limit Values
T
T
V
V
A
STG
DD
S
-40 to 85
– 65 to 150
4.2
-0.3 to V
(max. < 5.5)
Remarks
3 repetitions
2 repetitions, respectively
Electrical Characteristics
DD
PEF 80912/80913
+ 3.3
(Table
2001-03-29
17):
Unit
°C
°C
V
V
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