TMC2249AH5C Fairchild Semiconductor, TMC2249AH5C Datasheet - Page 5

• Manufacturer Part Number: TMC2249AH5C
• Manufacturer: Fairchild Semiconductor

Specifications of TMC2249AH5C

• Function: Digital Mixer
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Package Type: MQFP
• Pin Count: 120
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Compliant

TMC2249A
Pin Descriptions
REV. 1.0.2 7/6/00
Pin Name
Power
V
GND
Clock
CLK
Inputs
A
B
C
D
ADEL
BDEL
CDEL
DDEL
CAS
Controls
S
DD
11-0
11-0
15-0
11-0
11-0
15-0
3-0
3-0
3-0
3-0
B11, C10, A12,
B8, A8, B7, A7,
A6, B6, C6, A5,
G13, F13, F12,
E2, E1, F2, F1,
E3, G3, J3, L6,
B5, A4, C5, B4
A2, C4, B3, A1 117, 118, 119,
F3, H3, L7, C8 12, 20, 46, 102 Supply Voltage. The TMC2249A operates from a single +5V
N12, L10, M11
B12, C11, A13
M2, L3, N1, L2 32, 31, 30, 29
L13, K12, J11,
H2, J1, J2, K1,
K13, J12, J13,
F11, E13, E12
CPGA/PPGA/
L9, M10, N11,
C9, B10, A11,
N9, M9, N10,
A9, B9, A10,
M6, N5, M5,
N7, M7, N6,
G2, G1, H1,
C1, D2, D1,
N8, M8, L8,
N4, L5, M4,
N3, M3, L4
G12, G11,
L11, M12,
D11, B13,
H12, H13,
M13, K11
C13, D12
H11, C7
MPGA
K2, L1
C3
Pin Number
48, 49, 50, 51,
52, 53, 54, 55,
47, 45, 44, 43,
41, 40, 39, 38,
98, 97, 96, 95,
94, 93, 92, 91,
103, 104, 105,
107, 108, 109,
66, 67, 68, 69,
70, 71, 73, 74,
75, 76, 77, 78,
6, 7, 9, 10, 11,
13, 14, 15, 17,
18, 19, 21, 22,
56, 57, 58, 59
37, 36, 35, 34
110, 111, 112
113, 114, 115
61, 62, 63, 64
88, 87, 86, 85
79, 80, 81, 82
8, 16, 24, 42,
101, 100, 99,
23, 25, 26
72, 106
MQFP
120
90
1
Pin Function Description
supply. All power and ground pins must be connected.
Ground. The TMC2249A operates from a single +5V supply. All
power and ground pins must be connected.
System Clock. The TMC2249A operates from a single master
clock input. The rising edge of clock strobes all enabled registers.
All timing specifications are referenced to the rising edge of CLK.
A-D Input. A through D are the four 12-bit registered data input
ports. A
ports is clocked in to the top of the 16-stage delay pipeline on the
next clock when enabled, "pushing" data down the register stack.
A-D Delay. ADEL through DDEL are the four-bit registered input
data pipe delay select word inputs. Data to be presented to the
multipliers is selected from one of sixteen stages in the input data
delay pipe registers, as indicated by the delay select word
presented to the respective input port during that clock. The
minimum delay is one clock (select word=0000), and the maximum
delay is 16 clocks (select word=1111). Following powerup these
values are indeterminate and must be initialized by the user.
Cascade Input. CAS is the 16-bit Cascade data input port. CAS
the LSB. See Table 1.
Sum Output. The current 16-bit result is available at the Sum
output. The output may be the most or least significant 16 bits of the
current accumulator output, as determined by SWAP. S
See Table 1.
0
-D
0
are the LSBs (see Table 1). Data presented to the input
PRODUCT SPECIFICATION
0
is the LSB.
0
is
5