ISP1583BS,557 NXP Semiconductors, ISP1583BS,557 Datasheet - Page 14
ISP1583BS,557
Manufacturer Part Number
ISP1583BS,557
Description
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1583BS557.pdf
(100 pages)
Specifications of ISP1583BS,557
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / Rohs Status
Compliant
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ISP1583_7
Product data sheet
8.1 DMA interface, DMA handler and DMA registers
Table 4.
The ISP1583 operates on a 12 MHz crystal oscillator. An integrated 40
multiplier generates the internal sampling clock of 480 MHz.
The DMA block can be subdivided into two blocks: DMA handler and DMA interface.
The firmware writes to the DMA Command register to start a DMA transfer (see
The command opcode determines whether a generic DMA, Parallel I/O (PIO) or
Multi-word DMA (MDMA) transfer will start. The handler interfaces to the same FIFO
(internal RAM) as used by the USB core. On receiving the DMA command, the DMA
handler directs the data from the endpoint FIFO to the external DMA device or from the
external DMA device to the endpoint FIFO.
The DMA interface configures the timing and the DMA handshake. Data can be
transferred using either the DIOR and DIOW strobes or the DACK and DREQ
handshakes. DMA configurations are set up by writing to the DMA Configuration register
(see
For an IDE-based storage interface, applicable DMA modes are PIO and MDMA
(Multi-word DMA; ATA).
For a generic DMA interface, DMA modes that can be used are Generic DMA (GDMA)
slave.
Remark: The DMA endpoint buffer length must be a multiple of 4 bytes.
For details on DMA registers, see
Endpoint
identifier
EP0SETUP
EP0RX
EP0TX
EP1RX
EP1TX
EP2RX
EP2TX
EP3RX
EP3TX
EP4RX
EP4TX
EP5RX
EP5TX
EP6RX
EP6TX
EP7RX
EP7TX
Table 56
Endpoint access and programmability
and
Maximum packet
size
8 bytes (fixed)
64 bytes (fixed)
64 bytes (fixed)
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
Table
Rev. 07 — 22 September 2008
57).
Section
Double buffering Endpoint type
no
no
no
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
9.4.
Hi-Speed USB peripheral controller
set-up token
control OUT
control IN
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
© NXP B.V. 2008. All rights reserved.
Direction
OUT
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
ISP1583
PLL clock
Table
13 of 99
51).
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