ISP1583BS,557 NXP Semiconductors, ISP1583BS,557 Datasheet - Page 25
![no-image](/images/manufacturer_photos/0/4/487/nxp_semiconductors_sml.jpg)
ISP1583BS,557
Manufacturer Part Number
ISP1583BS,557
Description
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1583BS557.pdf
(100 pages)
Specifications of ISP1583BS,557
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / Rohs Status
Compliant
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NXP Semiconductors
ISP1583_7
Product data sheet
8.16.1 Power-sharing mode
As can be seen in
the 5 V-to-3.3 V voltage regulator. The input to the regulator is from V
supplied through the power source of the system. When the USB cable is plugged in, the
ISP1583 goes through the power-on reset cycle. In this mode, OTG is disabled.
The processor will experience continuous interrupt because the default status of the
interrupt pin when operating in sharing mode with V
this, implement external V
be connected to pin GPIO of the processor to qualify the interrupt from the ISP1583.
Remark: When the core power is applied, the ISP1583 must be reset using the RESET_N
pin. The minimum width of the reset pulse width must be 2 ms.
Fig 13. Power-sharing mode
Fig 14. Interrupt pin status during power off in power-sharing mode
V
CC(I/O)
is system powered.
V
V
CC(3V3)
V
V
Figure
CC(I/O)
CC(3V3)
CC(I/O)
Rev. 07 — 22 September 2008
INT
ISP1583
to GPIO of processor
for sensing V
13, in power-sharing mode, V
BUS
power off
RPU
V
BUS
sensing circuitry. The output from the voltage regulator can
1.5 k
BUS
REGULATOR
5 V-to-3.3 V
VOLTAGE
Hi-Speed USB peripheral controller
BUS
power off
CC(3V3)
not present is LOW. To overcome
V
1 µF
BUS
is supplied by the output of
004aaa459
1 M
BUS
© NXP B.V. 2008. All rights reserved.
USB
004aaa458
ISP1583
. V
CC(I/O)
is
24 of 99
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