ISP1583BS,557 NXP Semiconductors, ISP1583BS,557 Datasheet - Page 8
ISP1583BS,557
Manufacturer Part Number
ISP1583BS,557
Description
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1583BS557.pdf
(100 pages)
Specifications of ISP1583BS,557
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / Rohs Status
Compliant
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NXP Semiconductors
Table 3.
ISP1583_7
Product data sheet
Symbol
DACK
DIOR
DIOW
DGND
INTRQ
READY/
IORDY
INT
DA2
CS_N
[3]
[1]
Pin description
Pin
10
11
12
13
14
15
16
17
18
ISP1583BS ISP1583ET;
ISP1583ET2
F1
G2
G1
H2
H1
J1
K1
J2
K2
…continued
ISP1583ET1
E2
E3
F1
F2
G2
G1
H1
H2
E4
Rev. 07 — 22 September 2008
Type
I/O
I/O
I/O
-
I
I/O
O
O
I
[2]
Description
DMA acknowledge input or output (programmable
polarity); the signal direction depends on bit MASTER in
register DMA Hardware (see
When not in use, in the default setting, this pin must be
connected to V
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
DMA read strobe input or output (programmable polarity);
the signal direction depends on bit MASTER in register
DMA Hardware (see
When not in use, in the default setting, this pin must be
connected to V
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
DMA write strobe input or output (programmable polarity);
the signal direction depends on bit MASTER in register
DMA Hardware (see
When not in use, in the default setting, this pin must be
connected to V
bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant
digital ground
interrupt request input; from the ATA/ATAPI peripheral; use
a 10 k resistor to pull down
input pad; TTL; 5 V tolerant
Signal ready output — Used in generic processor mode:
I/O ready input — Used in split bus mode to access
ATA/ATAPI peripherals (PIO mode only)
bidirectional pad; 10 ns slew-rate control; TTL; 5 V tolerant
interrupt output; programmable polarity (active HIGH or
LOW) and signaling (edge or level triggered)
CMOS output; 8 mA drive
address output to select the Task File register of an
ATA/ATAPI device; see
CMOS output; 8 mA drive
chip selection input
input pad; TTL; 5 V tolerant
•
•
•
•
•
•
•
•
Input: DMA slave mode if bit MASTER = 0
Output: DMA master mode if bit MASTER = 1
Input: DMA slave mode if bit MASTER = 0
Output: DMA master mode if bit MASTER = 1
Input: DMA slave mode if bit MASTER = 0
Output: DMA master mode if bit MASTER = 1
LOW: the ISP1583 is processing a previous command
or data and is not ready for the next command or data
transfer
HIGH: the ISP1583 is ready for the next
microprocessor read or write
CC(I/O)
CC(I/O)
CC(I/O)
Hi-Speed USB peripheral controller
Table
Table
through a 10 k resistor.
through a 10 k resistor.
through a 10 k resistor.
Table 61
59):
59):
Table
59):
© NXP B.V. 2008. All rights reserved.
ISP1583
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