ISP1583BS,557 NXP Semiconductors, ISP1583BS,557 Datasheet - Page 38
ISP1583BS,557
Manufacturer Part Number
ISP1583BS,557
Description
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1583BS557.pdf
(100 pages)
Specifications of ISP1583BS,557
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / Rohs Status
Compliant
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NXP Semiconductors
Table 32.
ISP1583_7
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Interrupt Enable register: bit allocation
IEVBUS
IEP6TX
IEP2TX
R/W
R/W
R/W
31
23
15
0
0
0
0
7
0
0
-
-
-
Table 33.
Bit
31 to 26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
IEP6RX
IEP2RX
IEDMA
R/W
R/W
R/W
30
22
14
0
0
0
0
6
0
0
-
-
-
Interrupt Enable register: bit description
Symbol
-
IEP7TX
IEP7RX
IEP6TX
IEP6RX
IEP5TX
IEP5RX
IEP4TX
IEP4RX
IEP3TX
IEP3RX
IEP2TX
IEP2RX
IEP1TX
IEP1RX
IEP0TX
IEP0RX
-
IEP0SETUP
IEHS_STA
IEP5TX
IEP1TX
R/W
R/W
R/W
29
21
13
0
0
0
0
5
0
0
-
-
-
Rev. 07 — 22 September 2008
reserved
Description
reserved
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from the indicated endpoint.
Logic 1 enables interrupt from control IN endpoint 0.
Logic 1 enables interrupt from control OUT endpoint 0.
reserved
Logic 1 enables interrupt for the set-up data received on endpoint 0.
IERESM
IEP5RX
IEP1RX
R/W
R/W
R/W
28
20
12
0
0
0
0
4
0
0
-
-
-
IESUSP
IEP4TX
IEP0TX
R/W
R/W
R/W
27
19
11
0
0
0
0
3
0
0
-
-
-
Hi-Speed USB peripheral controller
IEPSOF
IEP4RX
IEP0RX
R/W
R/W
R/W
26
18
10
0
0
0
0
2
0
0
-
-
-
reserved
IEP7TX
IEP3TX
IESOF
R/W
R/W
R/W
25
17
0
0
0
0
9
1
0
0
-
-
-
© NXP B.V. 2008. All rights reserved.
ISP1583
IEP0SETUP
IEP7RX
IEP3RX
IEBRST
R/W
R/W
R/W
R/W
24
16
0
0
0
0
8
0
0
0
0
1
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